I have some questions about the component:
1. what should be the input configuration to get into osc-in in LVDS format?
2. In the D\S is mentioned:
For a 2.1 V commonmode, 50 Ω single-ended source, the input limit of 2.8 V allows ~700 mV of amplitude, or 6 dBm of maximum reference power.
My question is about the differential input. Does The limit of 1.4Vp-p is differential or refer to each leg (which bring us to 2.8Vp-p differential)?
3. What should I connect to the unused leg for single-ended input (A or B configuration)?
1) For AC coupled LVDS input, you need to enable AC coupled input, disable 100 ohm internal termination and enable Hi-Z input. Also, you need to put 100 ohm termination resistance between positive…
what is the signal to signal jitter of the same output (using an external VCO input)?
1) For AC coupled LVDS input, you need to enable AC coupled input, disable 100 ohm internal termination and enable Hi-Z input. Also, you need to put 100 ohm termination resistance between positive and negative legs before AC coupling.
For DC coupled LVDS input, you need to disable AC coupled input, disable 100 ohm internal termination and enable Hi-Z input. Also, you need to put 100 ohm termination resistance.
2)Internal supply voltage is 2.8V for the buffers. The requirement is not to exceed 2.8 V at each pin for both single ended and differential.
3)Unused leg should be directly connected to the ground with 100nF, configuration B is the correct one.
What is the minimum level of clockin signal in 1920MHz?
Is it still 0.375Vpp?
For 1920 MHz clockin signal, I assume you are asking for external VCO input. It is specified in Table 5 as min -6 dBm and max 6 dBm.
If you are considering to use 1920 MHz signal as PLL1 reference, maximum frequency spec is 800 MHz as given in Table 4.
What is the skew of clock/sclock output signal?
I saw in the D/S that the skew between clock and sclock is about 15ps. But what ia the skew of the clock to himself?
Channel to channel skew varies depending on whether they are in same clock group or they are sharing same supply. Depending on these, channel to channel skew may vary up to 30ps.
Do you mean the skew between positive and negative outputs of the channel?
This value is very critical in our project