Hello - I am trying to implement the refclk/sysref distribution scheme shown in the LTC6953 datasheet on pg. 54. The LTC6952 datasheet specifies the relationship between the IN± and EZS_SRQ± lines in PARSYNC mode. The LTC6953 doesn't support PARSYNC mode and only lists a typical minimum time of 1ms to assert EZS_SRQ±.
Is the SYSREF signal at the end of the chain (stage 3 on page 54) guaranteed to assert on the same clock edge across the entire array of stage 2 devices?
Thanks,
Nick
Hey Nick,
I apologize, I looked at page 53. Page 54 is the 3 stage Sync example. Jon is going to setup a call. I need to look on my computer for the code I used to perform this. I think that will be the most straight forward thing to follow. I'll need a day to locate the code... 
Nick,
I think the short answer is it uses the passthru mode.
In the LTC6952Wizard, you can select 'File --> Load Settings'. In the 'LTC6952 Typical Applications' there are 3 files, that provide the initial state for the 3 stage parallelsync example.
From there you should be able to follow the steps in the datasheet (page 55 ltc6953, or page 77 ltc6952 datasheet), for programming instructions.
Below is a snippet of Arduino code that I used for this example. I've also attached the original Arduino code, but you'll need to download the LTSketchbook from analog.com to use this (For the support files). You can put these directory structure in the LTSketchbook WIP folder. (Note this uses the DC2430 board connected to 3 LTC6953s and 2 LTC6952s) https://www.analog.com/media/en/dsp-documentation/evaluation-kit-manuals/DC2430AF.PDF
/* ---------------------------------------------------------------------
ParallelSync_3Stage_SyncPassthru() - Function performs the 3 Stage
ParallelSync with Pass thru. See datasheet for block diagram.
--------------------------------------------------------------------- */
void ParallelSync_3Stage_SyncPassthru() {
uint8_t LTC695x_lkup_tbl[5][LTC695x_NUM_REGADDR] = { //!< the following settings assume a 100MHz reference input
#if 1
/* these register settings are for a typical use case */
/* LTC6953 stage 1, DC2430 site 0 */ {0x25, 0x88, 0x02, 0xff, 0xf0, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x08, 0xc0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x08, 0xc0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13},
/* LTC6953 #1 stage 2, DC2430 site 3 */ {0x25, 0x88, 0x00, 0xff, 0xf0, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x08, 0xc0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x80, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13},
/* LTC6953 #2 stage 2, DC2430 site 4 */ {0x25, 0x88, 0x00, 0xff, 0xf0, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x08, 0xc0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x80, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13},
/* LTC6952 #1 stage 3, DC2430 site 6 */ {0x15, 0xaa, 0x08, 0x22, 0x82, 0x08, 0xcc, 0x01, 0x00, 0x28, 0x13, 0x06, 0x9c, 0xe0, 0x18, 0x00, 0x38, 0x80, 0x20, 0x00, 0x9c, 0xe0, 0x18, 0x00, 0x38, 0x80, 0x20, 0x00, 0x9c, 0xe0, 0x00, 0x00, 0xf8, 0x80, 0x20, 0x00, 0x99, 0x80, 0x00, 0x00, 0x9c, 0xe0, 0x1f, 0x00, 0x00, 0x80, 0x20, 0x00, 0x9c, 0xe0, 0x1f, 0x00, 0x00, 0x80, 0x20, 0x00, 0x12},
/* LTC6952 #2 stage 3, DC2430 site 7 */ {0x15, 0xaa, 0x08, 0x22, 0x82, 0x08, 0xcc, 0x01, 0x00, 0x28, 0x13, 0x06, 0x9c, 0xe0, 0x18, 0x00, 0x38, 0x80, 0x20, 0x00, 0x9c, 0xe0, 0x18, 0x00, 0x38, 0x80, 0x20, 0x00, 0x9c, 0xe0, 0x00, 0x00, 0xf8, 0x80, 0x20, 0x00, 0x99, 0x80, 0x00, 0x00, 0x9c, 0xe0, 0x1f, 0x00, 0x00, 0x80, 0x20, 0x00, 0x9c, 0xe0, 0x1f, 0x00, 0x00, 0x80, 0x20, 0x00, 0x12}
}; //!< LTC6952 Configuration look-up table
#else
/* these register settings had dividers at every stage of the reference path - used to prove out worst case sync methods */
/* LTC6953 stage 1, DC2430 site 0 */ {0x25, 0x88, 0x00, 0xff, 0xf0, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x80, 0x00, 0x00, 0x08, 0xc0, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x80, 0x00, 0x00, 0x08, 0xc0, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13},
/* LTC6953 #1 stage 2, DC2430 site 3 */ {0x25, 0x88, 0x00, 0xff, 0xf0, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x80, 0x00, 0x00, 0x08, 0xc0, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x80, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13},
/* LTC6953 #2 stage 2, DC2430 site 4 */ {0x25, 0x88, 0x00, 0xff, 0xf0, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x80, 0x00, 0x00, 0x08, 0xc0, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 0x80, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13},
/* LTC6952 #1 stage 3, DC2430 site 6 */ {0x15, 0xaa, 0x08, 0x22, 0x82, 0x08, 0xcc, 0x02, 0x01, 0x40, 0x13, 0x06, 0x9c, 0xe0, 0x18, 0x00, 0x38, 0x80, 0x20, 0x00, 0x9c, 0xe0, 0x18, 0x00, 0x38, 0x80, 0x20, 0x00, 0x9c, 0xe0, 0x00, 0x00, 0xf8, 0x80, 0x20, 0x00, 0x99, 0x80, 0x00, 0x00, 0x9c, 0xe0, 0x1f, 0x00, 0x00, 0x80, 0x20, 0x00, 0x9c, 0xe0, 0x1f, 0x00, 0x00, 0x80, 0x20, 0x00, 0x12},
/* LTC6952 #2 stage 3, DC2430 site 7 */ {0x15, 0xaa, 0x08, 0x22, 0x82, 0x08, 0xcc, 0x02, 0x01, 0x40, 0x13, 0x06, 0x9c, 0xe0, 0x18, 0x00, 0x38, 0x80, 0x20, 0x00, 0x9c, 0xe0, 0x18, 0x00, 0x38, 0x80, 0x20, 0x00, 0x9c, 0xe0, 0x00, 0x00, 0xf8, 0x80, 0x20, 0x00, 0x99, 0x80, 0x00, 0x00, 0x9c, 0xe0, 0x1f, 0x00, 0x00, 0x80, 0x20, 0x00, 0x9c, 0xe0, 0x1f, 0x00, 0x00, 0x80, 0x20, 0x00, 0x12}
}; //!< LTC6952 Configuration look-up table
#endif
uint8_t LTC695x_Site_list[5] = {0,3,4,6,7}; /* site mirrors look up LTC695x_lkup_tbl location */
uint16_t DC2430_Site_list[8] ={6953,-1,-1,6953,6953,-1,6952,6952};
uint8_t DC2430_ParallelSync_StageNum[8] = {1,-1,-1,2,2,-1,3,3};
uint8_t DC2430_ParallelSync_DevNum[8] = {1,-1,-1,1,2,-1,1,2};
uint8_t *rx; /* for SPI writes */
uint8_t val_temp; /* for SPI writes */
int array_loc;
uint8_t field_num;
long field_val;
uint16_t user_command; // User input command
/* STEP 1: VERIFY DEMO BOARD CONNECTIONS ARE CORRECT */
DC2430_Bin = 1; // initialize DC2430_Bin
/* confirms DC2430 & DC2026 uses the correct settings */
DC2430_test_supply(); // if DC2430 connect and setup properly, then returns global DC2430_Bin=1
DC2430_SiteCheck(DC2430_Site_list,DC2430_ParallelSync_StageNum,DC2430_ParallelSync_DevNum);
// if DC2430 connect and setup properly, then returns global DC2430_Bin=1
Serial.flush();
if (DC2430_Bin==1) {
/* STEP DEBUG: Set all devices to Power up state */
for (array_loc=0; array_loc<5; array_loc++) {
changeDC2430site(LTC695x_Site_list[array_loc]); // switch DC2430 site
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_POR, 1); /* resets all devices every run */
} /* end of for loop - array_loc... */
/* STEP 2: Program Initial SPI settings for all LTC695x parts */
for (array_loc=0; array_loc<5; array_loc++) {
LTC695x_lookuptbl_write(array_loc,LTC695x_Site_list,LTC695x_lkup_tbl);
} /* end of for loop - array_loc... */
/* STEP 3: SYNCRONIZE OUTPUT STAGES and 2 by toggling the Stage 1 LTC6953 SSRQ bit in addr 0x0B */
Serial.println(F("\n\nInitial Registers Loaded: "));
Serial.println(F("Press <ENTER> to sync (EZSync) STAGE 1&2 reference outputs: "));
user_command = read_int(); //! Reads the user command
changeDC2430site(0); // switch DC2430 site
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_SSRQ, 1);
delay(1); // min 1ms delay for SSRQ HIGH pulse
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_SSRQ, 0);
delay(1); // min 1ms delay for SSRQ LOW pulse
/* OPTIONAL STEP 4a1: ADJUST STAGE 1 ADEL values if desired, this lines up the reference edges at the STAGE 2 inputs,
will need to resync as this can cause the follower input to glitch */
/* OPTIONAL STEP 4a2: ADJUST STAGE 2 ADEL values if desired, this lines up the reference edges at the STAGE 3 inputs,
no resync necessary */
/* **** PARALLEL SYNC STAGE 3. THIS IS DONE BY STEPS 5-7
5) this is done by enabled SRQMD=1, which will retime STAGE 1 & STAGE 2 PASS-THRU OUTPUTS to
the input reference signal
6) disabled SQEN for on ALL STAGE 1 and 2 CLOCK OUTPUTS
7) Toggle STAGE 1 SSRQ BIT, this will ParallelSync the STAGE 3 outputs */
Serial.println(F("\nStage 2 REFERENCES synchronized: "));
Serial.println(F("Press <ENTER> to sync (ParallelSync) STAGE 3 clock outputs: "));
user_command = read_int(); //! Reads the user command
for (array_loc=0; array_loc<=2; array_loc++) {
changeDC2430site(LTC695x_Site_list[array_loc]); // switch DC2430 site
// STEP 5. this is done by enabled SRQMD=1, which will retime STAGE 1 & STAGE 2 PASS-THRU OUTPUTS to the input reference signal
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_SRQMD, 1);
// STEP 6. disabled SQEN for on ALL STAGE 1 and 2 CLOCK OUTPUTS
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_SRQEN4, 0);
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_SRQEN8, 0);
} /* end of for loop - array_loc... */
// STEP 7. Toggle STAGE 1 SSRQ BIT, this will ParallelSync the STAGE 3 outputs
changeDC2430site(0); // switch DC2430 site
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_SSRQ, 1);
delay(1); // min 1ms delay for SSRQ HIGH pulse. ***
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_SSRQ, 0);
delay(1); // min 1ms delay for SSRQ LOW pulse
/* **** SEND SYSREF FROM STAGE 3. THIS IS DONE BY STEPS 8-10
8) Power up STAGE 3 SYSREF outputs (PDx=0)
9) Set all STAGE 3 LTC6952 SRQMD=1
10) Toggle STAGE 1 SSRQ BIT, this will ParallelSync the STAGE 3 outputs */
Serial.println(F("\nStage 3 OUTPUTS synchronized: "));
Serial.println(F("Press <ENTER> to send Stage 3 SYSREF PULSES: "));
user_command = read_int(); //! Reads the user command
for (array_loc=3; array_loc<=4; array_loc++) {
changeDC2430site(LTC695x_Site_list[array_loc]); // switch DC2430 site
// STEP 8. Power up STAGE 3 SYSREF outputs (PDx=0)
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_PD0, 0);
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_PD2, 0);
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_PD4, 0);
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_PD7, 0);
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_PD9, 0);
// STEP 9. Set all STAGE 3 LTC6952 SRQMD=1
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_SRQMD, 1);
} /* end of for loop - array_loc... */
delay(1); // delay min of 50us for SYSREF pins to power up.
// STEP 10. Toggle STAGE 1 SSRQ BIT, this will ParallelSync the STAGE 3 outputs
changeDC2430site(0); // switch DC2430 site
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_SSRQ, 1);
delay(1); // min 1ms delay for SSRQ LOW pulse
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_SSRQ, 0);
delay(1); // min 1ms delay for SSRQ LOW pulse
// OPTIONAL STEP 11. Power down STAGE 3 SYSREF outputs (PDx=2)
Serial.println(F("\nSYSREF PULSES SENT: "));
Serial.println(F("Press <ENTER> to power down SYSREF outputs and set SRQMD=0: "));
user_command = read_int(); //! Reads the user command
for (array_loc=3; array_loc<=4; array_loc++) {
changeDC2430site(LTC695x_Site_list[array_loc]); // switch DC2430 site
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_PD0, 2);
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_PD2, 2);
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_PD4, 2);
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_PD7, 2);
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_PD9, 2);
} /* end of for loop - array_loc... */
// STEP 12. Set SRQMD=0 to save Power ~300mW per device
for (array_loc=0; array_loc<5; array_loc++) {
changeDC2430site(LTC695x_Site_list[array_loc]); // switch DC2430 site
set_LTC6952_SPI_FIELD(QUIKEVAL_CS, LTC695x_SRQMD, 0); /* resets all devices every run */
} /* end of for loop - array_loc... */
} /* end of if DC2430_Bin == 1 */
}
Hi Chris!
I need technical support about LTC6952 and LTC6953 “ParallelSync Multi-Chip Synchronization with Request Passthrough” three stage configuration (according to LTC6952 datasheet page 76). I would like to know if is it possible to connect in a daisy-chain configuration those chips placed on different boards as shown below:
Can I try this configuration using LTC6952Wizard, DC2026 board, DC2430A exapansion board, 3 x DC2610A boards and 3 x DC2609A boards? Are there just available some .6952set files in LTC6952Wizard tool to try this configuration? What's the maximum number of different boards in daisy-chain configuration to ensure a good synchronization? Thank you so much.
Best Regards
Antonio
Chris,
in my configuration I would like to connect a maximum of 10 slaves to a master. I don't care how long it takes because I suppose this multi stage synchronization is only in a startup phase. Is it true? Or do I must periodically refresh it?
A single board can work standalone if not connected in a distributed system.
I'm going to show you the real configuration I would like to do:
In general do you confirm me that I can try this with those evaluation boards (LTC6952Wizard, DC2026 board, DC2430A exapansion board, n x DC2610A boards and n x DC2609A boards)? Am I evaluating the right configuration to my project scope?
Thank you.
Antonio
