I want to use AD9545 to output 1.8V CMOS single-ended mode, but I see from the specification that it only supports HCSL and CML single-ended mode, and the level is only around 0.7V, page 18.I want to output 1.8V CMOS single terminal, what should I do?
1、what should I do with the unused output of AD9545 and AD9508? Float?
2、I am going to use a TCXO as system clock compensation in M0_PIN, but I am not sure about the parameter requirements of this TCXO, could you tell me the parameter requirements of TCXO?Do you have a TCXO recommendation?
3、It is mentioned in page 50 of AD9545 datasheet that 1PPS needs a low loop bandwidth, otherwise the DPLL will be unlocked, and 1PPS synchronization needs a system clock compensation, but I don't quite understand how the system clock compensation enables the DPLL to get low loop bandwidth？Please help me to understand.
yes, float the outputs and use the software bits to power down the drivers.
Use a low frequency TCXO (10MHz is a good choice) as the system clock compensation reference. The characteristics are determined by how stable you want the outputs to be when the DPLLs are in holdover.
1PPS DPLL bandwidth should be 50 mHz. This means that low frequency effects on the DPLL inputs will be reflected on the outputs. A digital DPLL has the reference clock as the input. But also the system clock is an input because the system clock clocks the DPLL. So having a system clock that "wonders", basically based on a very low frequency component, creates a wonder on the output as well. This wonder may move the phase (and in worst situations the frequency as well) of the output. So the DPLL status may wonder between a lock status and an unlock status. Try it yourself and you will see it with the evaluation board using the crystal.
Then, when the DPLL is in holdover, the stability of the output is determined by the stability of the system clock, so you want the system clock to be as stable as the OCXO (or TCXO). This is what the system clock compensation accomplishes.