Does AD9545 support 1.8V CMOS single-ended output mode?

Hi,

   I want to use AD9545 to output 1.8V CMOS single-ended mode, but I see from the specification that it only supports HCSL and CML single-ended mode, and the level is only around 0.7V, page 18.I want to output 1.8V CMOS single terminal, what should I do?

   thanks!

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    •  Analog Employees 
    on Jun 17, 2020 3:02 PM in reply to ed592

    Hi,

    these are my observations on that schematic:

    - the AD9545 SYSCLK is at 25 MHz. I suppose this is a crystal resonator. I recommend using a 52 MHz (like our eval board, but you could use one up to 60MHz) because the phase noise of the outputs is better when the crystal frequency is higher.

    - system clock compensation using a TCXO is great.

    - not clear to me which DPLL phase buildout or internal zero delay mode is used for the two DPLLs. Anyway, the 10 MHz and 100 MHz outputs are aligned because they come from the same DPLL0 and 122.88MHz is by itself coming from DPLL1 and because 122.88MHz is prime relative to 100MHz its alignment does not matter.

    - you may think to use one AD9508 for the 100 MHz output and derive the 10 MHz CMOS outputs from it. You would use the divide by 10 option. You would need to use the SPI or I2C port to program the AD9508 as the divide by 10 option does not exist for pin strapping. There is a propagation delay for CMOS outputs of 2.56 ns typ and a skew between the outputs of max 112 ps. You can compensate for the typical propagation delay in the AD9545 distribution output (see distribution phase offset control section in the AD9545 data sheet) or in the DPLL (see the DPLL phase offset section. This would be meaningful when Internal zero delay is used)

       

    In this case, the skew between chips of max 965 ps does not matter as you have only one AD9508 that produces the 100 MHz and 10 MHz.

    - Same considerations about the propagation delay apply for the 30.72 MHz and 122.88MHz outputs. Here you can use the pin strapping as the divider is 4.

    Petre

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