LTC6951: No Lock, no calibration


We are designing in a LTC6951 to provide clocks for ADC and FPGA.

Independent of clock settings (either those from data sheet examples with external clock as well as with own settings) we always get the following error image:

VCO obviously is somewhere around 4.22 GHz

Lock detect error is detected: Register  00 is h49.

Register 02 is h01, i.e. LSB remains "1" (CAL = 1) whenever Calibration oder autocalibration shall be executed. Our application operates with reference clock 38,4 MHz, Loop filter variant 2 (from LTC6951 wizard) with c2 = 1 nF, R1 and RZ 100 Ohm, Ci 68 nF, Cp 1.5 nF.

Register programming is as follows:

Reg-No / Reg Value:

h01 h72

h02 h00

h03 h78 (also tested with 70)

h04 h83

h05 h04

h06 h78

h07 h07

h08 h00

h09 hD9

h0A h00

h0B h95

h0C h00

h0D hD9

h0E h00

h0F h32

h10 h00

h11 h32

h12 h00

We do NOT use multiple byte transfer on SPI, but single byte transfer. Each register setting has been checked using read commands.


We tested this on two boards to exclude the possibility of singe part failure.


Any advice?

Best regards,

Ulrich Hilsinger

  • 0
    •  Analog Employees 
    on May 4, 2020 12:41 PM

    Hi Ulrich,

    I believe your company has sent a similar question through the local FAE, Olim.  I sent him a response to this question this weekend.  Let me know if this is not the case.

    Below is the response I sent him

    I noticed a few things, but I think the most important one to fix is the reference inputs.  The DC voltage on both REF+ and REF- should be around 1.85V.

    Here are some recommended schematics

    Here are some other items you could look at.

    You chose some good LDOs.  However, I think they need a larger voltage between input and output.  The closer the LDO voltage between input and output the worse the PSRR.

    If the LDOs are driven by a switching supply, then a larger power supply switching spur will not be rejected by the PSRR with small drop out voltages.  I’d recommend >500mV between the input and output of the LDO.

    I could not find the reference’s datasheet.  But based on its small footprint I suspect it’s phase noise is higher than was modelled in the LTC6951Wizard to develop the loop filter.  Based on other references in that pkg size, I’m providing t a 90kHz BW loop filter.



  • Thank you for your response, Chris. We also got a response through the FAE.

    Of course, the missing AC decoupling has been the fault. The register 00 output (LSB = 1) made us to not verify the input circuitry again that deep.

    Regarding loop filter and phase noise, with the values of our TCXO (-134 dBc at 1 kHz, Noise floor -156 dBc/Hz) we get an optimum noise bandwidth of 168 kHz from the wizard, while noise plot values are fitting better to our requirement specification (which are especially stringent for offsets equal to or below 100 kHz) if we set the bandwidth even higher.

    Thank you.


  • 0
    •  Analog Employees 
    on May 5, 2020 12:47 AM in reply to UlrichHilsinger


    Glad the reference cap was the fix.  Yes, the ref detect circuit is fairly sensitive, which can be either a good or bad thing.

    I calculated a similar loop BW with those number provided above.



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