Few months ago we were discussing Clock distribution of ultra low noise OCXO where we were interested in possible phase noise performace on offsets 10Hz to 1kHz.
We have done some measurements and now we are considering only LTC6957 as direct clock buffer into ADc. The LTC6953 is not suitable for our requirements because of additive phase noise at low offsets 10Hz to 1kHz. Other vendors ICs are much worse...
We need to clock 4 ADc without phase noise degradation and some reference clocks for FPGA where phase noise performance is no care.
So here comes the question:
Can LTC6957 be used in clock tree in parallel combination?
Our first idea is to feed 3x LTC6957 without a power splitter where 150ohm resistors are placed on each input, so the source clock (OCXO with sinus 10dBm/50ohm) "sees" 50ohm load. 3-port power splitter usage could require low noise amplifier to compensate the 6dB loss.
What do you think?