Post Go back to editing

LTC6957 parallel clock tree


Few months ago we were discussing Clock distribution of ultra low noise OCXO where we were interested in possible phase noise performace on offsets 10Hz to 1kHz.

We have done some measurements and now we are considering only LTC6957 as direct clock buffer into ADc. The LTC6953 is not suitable for our requirements because of additive phase noise at low offsets 10Hz to 1kHz. Other vendors ICs are much worse...

We need to clock 4 ADc without phase noise degradation and some reference clocks for FPGA where phase noise performance is no care.

So here comes the question:

Can LTC6957 be used in clock tree in parallel combination?

Our first idea is to feed 3x LTC6957 without a power splitter where 150ohm resistors are placed on each input, so the source clock (OCXO with sinus 10dBm/50ohm) "sees" 50ohm load. 3-port power splitter usage could require low noise amplifier to compensate the 6dB loss.

What do you think?



  • Hi Daniel,

    Here is a plot of the LTC6955, does this not work for the 125MHz OCXO phase noise targets mentioned in the last email?  Or do you have some tougher requirements?

    This below plot compares the Pascal 100MHz OCXO direct --> E5052 vs the PASCA 100MHz OCXO --> variable attenuator --> LTC6955 --> E5052.

    For this plot I did not have the E5052 correlation settings high enough to measure the Pascal's or LTC6955 true close in performance shown in the Pascal datasheet.  This plot shows pessimistic results.   There are also some spurs in these plots coming from somewhere else (probably not the part or the OCXO).

    The LTC6955 can have any combination of 3 -11 differential CML outputs turned on.

    Regarding the LTC6957 comments.  I do agree adding the LNA adds its own set issues, as Low Noise Amplifier often does not mean Low Phase Noise Amplifier.  I think the 150 ohm resistor idea could work, but I haven't tried it.  


  • Hi Daniel,

    One other thought is the LTC6954.  It has 6 outputs pins (3 differential, or 6 CMOS, or some combination CMOS/differential).  It is in the same family as the LTC6957, but with more outputs and its programmable.  If you were thinking of using CMOS outputs, then maybe one LTC6945 does the job of three LTC6957s?


Reply Children
  • Hello Chris,

    thank you very much for the plot of the LTC6955.

    I can't precisely specify phase noise requirements because of proprietary stuff but we can communicate it through email if you want.

    Do you have a phase noise specification of used Pascal OCXO? Datasheet says there are 6 level grades of phase noise performance (level E, 1-6).

    Regarding LTC6954 it looks promising. Does it handle sine wave as LTC6957 translator? I suppose the combination of LTC6954/7 and LTC6953 (as slave of last LTC6954/7s output) can't be compatible with proper generation SYSREF signals, because both devices can't be proper synchronized, am I right?

    We will reconsider requirements for clocking two ADc instead the four ADc.



  • sent you a direct mssg. to discuss off the public forum