I'm using the AD9434 working at 500MSPS in the DDR data mode, which will be captured by FPGA.
In the FPGA design, the input timing constraint needs to be made. Through the datasheet, only a Tkew parameter is found, but the other key parameters, relative to the timing, such as Tsetup and Thold, are not found. Usually, the Tsetup and Thold constitute of the data valid window, which is my focus.
So, could you tell the Tsetup and Thold time or is there any other way to constrain the timing for FPGA when utilizing AD9434?
There is no guaranteed setup and hold time for this device. The clock and data transition simultaneously, and the guaranteed specification is that the skew between these transitions is +/-70ps. You will need to delay the clock or data within the FPGA to create the necessary setup and hold time.
I would like to confirm something about the register 0x17 FLEX_OUTPUT_DELAY. When shifting the DCO by 3/10 clock period in DDR output, does it mean the clock edge nearly falls in the middle of the data, the same as a phase shifting? In this case, skew will keeps +/-70ps or +/-70ps pluses 3/10 clock period?
That is the intended behavior, but there is no data to support that in the data sheet. If your receiver circuit has a guaranteed delay feature, I would recommend that.