AD9434 setup and hold time for data

Hi,

I'm using the AD9434 working at 500MSPS in the DDR data mode, which will be captured by FPGA.

In the FPGA design, the input timing constraint needs to be made. Through the datasheet, only a Tkew parameter is found, but the other key parameters, relative to the timing, such as Tsetup and Thold, are not found. Usually, the Tsetup and Thold constitute of the data valid window, which is my focus.

So, could you tell the Tsetup and Thold time or is there any other way to constrain the timing for FPGA when utilizing AD9434?

Regards,

Chunjie

Parents Reply Children
No Data