Good Afternoon,
I am currently working with a multi-chip synchronization architecture with one (1) LTC6952 as my controller feeding two (2) LTC6953s as my followers. I am trying to verify the synchronization is functioning as I would expect with the DC2609A and DC2610A and am running into a few issues with consistency.
I have provided a simple block diagram of my setup below for reference:

Ref CLK: 100MHz onboard Crystek oscillator
Green Trace: AC coupled single ended 4GHz clock output from LTC6952 to Ref CLK input to LTC6953
Purple Trace: DC coupled, 100 Ohm terminated 500MHz clock output from LTC6952 to EZSync inputs on LTC6953
Black Trace: AC coupled 4GHz output clock from LTC6953
Red Trace: AC coupled 500MHz SYSREF output from LTC6953
NOTE: All clock outputs from LTC6952/LTC6953 are set to divide by 1. All SYSREF outputs from LTC6852/LTC6953 are set to divide by 8.
What I am currently seeing is a consistent 1 clock cycle skew between SYSREF outputs between my two boards. I can not seem to get the SYSREFs to align on the same clock edge no matter what I try with the evaluation boards. The GUI itself does not offer much confidence that the changes being made are actually being enacted on the device, so that could be part of my problem. In general I have a few questions regarding this setup however that I am hoping someone can help resolve.

Yellow Trace: CLK output from LTC6953 #1
Green Trace: SYSREF output from LTC6953 #1
Orange Trace: CLK output from LTC6953 #2
Blue Trace: SYSREF output from LTC6953 #2
Questions:
1. Is this a valid setup? I see the reverse mentioned several times, but never a 52 feeding 53s.
2. Why do my SYSREF signals transition on the rising edge of the clock output and not the falling?
3. The LTC6953 datasheet page 20 mentions "For all cases of EZSync synchronization, the CONTROLLER must be programmed to output seven pre-pulses to each FOLLOWER before the FOLLOWER outputs or any follower-synchronous CONTROLLER outputs start clocking." Is this possible with the LTC6952 without doing a pure pass through from a logic device? If no, am I expected to use a logic device to accomplish this?
4. The LTC6953 datasheet page 16 mentions "The EZS_SRQ input state or SSRQ bit must remain high for a minimum of 1ms.". How is this intended to be accomplished with my current setup? With a 4GHz VCO frequency this does not seem achievable with a max divide ratio of 4096 on the outputs. I presume the digital sync is not deterministic, but I hope the EZSync inputs can be for repeat behavior.
5. Using the GUI the synchronization routine is not very clear. I see in the LTC6952 datasheet there is a programming and sync guide (shown below), but I have to be very careful how I program these devices as often I will not get any response from SYSREF outputs if the sync is not performed correctly. Do you have a recommendation for how to synchronize my setup?
LTC6952 Datasheet page 74

I would like to be able to power cycle these boards and easily repeat this exercise of synchronization but I am not able to do this at the moment. Any feedback that can be offered would be greatly appreciated. If there are any questions about what I have mentioned I would be happy to answer them.
Regards,
Aaron
