Hi, thanks in advance for your attention and reply.
I now want to use two AD9516-1 chips on two different boards, and I want to synchronize the output of the two chips.
For example, two AD9516-1's out0 ports output 250MHZ signals. I want their phases / timings to be aligned. Let me talk about the work I am doing and the problems I have encountered.
1. Below is my block diagram. A signal source generates a signal with a frequency of 1 GHz, and then enters two ADCLK 925 after passing through the power divider. It is then entered into two AD9516-1. Both 9516 SYNC pins are connected to a switch through a buffer. The AD9516-1 does not use a VCO divider internally. It directly inputs from the CLK and then passes through the channel divider. The output is obtained after dividing by 4. My idea is that when I press the switch, the output of the two AD9516-1s can achieve alignment.
2. As a matter of fact, when I press the switch, their output is not aligned. The yellow and green lines are the output signals from two different ad9516-1. As shown in the three pictures below. As can be seen from the figure, the output has several states, and alignment is one of them. When I press the switch repeatedly, many things happen. In other words, my idea cannot achieve the alignment of the two 9516 pieces.
3. So, is it possible to achieve output alignment between different AD9516-1? If so, how should it be achieved? Is the idea I mentioned above feasible or completely impossible?
Many thanks. Wu
the problem you have is outlined in the data sheet, page 46: "there is an uncertainty of up to one cycle of the clock at the input to the channel divider due to asynchronous nature of SYSC signal with respect to the clock edges inside the AD9516". This is why every time you toggle SYNC pin you get different synchronization situations.
I propose the following approach:
Use ADCLK905 buffer (you need only one output, not two like ADCLK925) to create the 1 GHz CLK+/- inputs to AD9516-5 (no need to have an internal VCO if you do not use it). Use OUT8 and OUT9 that can be set as LVDS outputs to enter into the second AD9516-5 CLK+/- inputs.
Do the following operations:
- set bit 0 (Soft SYNC) to 1 in register 0x230 of both AD9516s. This is equivalent to bringing SYNC pin low on both chips.
- clear bit 0 (Soft SYNC) to 0 in register 0x230 of the bottom AD9516. This is equivalent to bringing SYNC pin of the bottom AD9516 high and synchronizing all the outputs of the bottom AD9516.
- clear bit 0 (Soft SYNC) to 0 in register 0x230 of the top AD9516. This is equivalent to bringing SYNC pin of the top AD9516 high and synchronizing all the outputs of the top AD9516. Because the OUT8/OUT9 clock flows "unobstructed" into the bottom AD9516, all outputs from both chips will be synchronized.
Thanks Petre.Thanks for your advice.
Yes, I saw "there is an uncertainty of up to one cycle of the clock at the input to the channel divider due to asynchronous nature of SYSC signal with respect to the clock edges inside the AD9516" in the data sheet, but I later felt that this sentence should not affect any results. The reason for the uncertainty of a clock cycle is that when the sync pin signal changes to high level, it may just enter a new cycle for the "input to channel divider". At this time, it needs a delay of 15 cycles.If the "input to channel divider" has already entered the next cycle at this time, it should only need a delay of 14 cycles.So it is because of the uncertainty of the state of “input to channel divider” when the SYNC pin is high.It is shown in the red box in the figure below.
The reason why I think this method works is that when I press sync, the "output of channel dividers" should be aligned with "input to VCO dividers" or "input to CLK". When I bypass the VCO divider, "out of channel provider" should be aligned with "input to CLK". At this time, a signal is input to the CLK port of 9516 after passing through the power divider. If I guarantee that this path is the same length, does that mean that the CLK input of 9516 is aligned? Then press the sync key and release it, the sync signals of the two 9516 chips will be pulled up at the same time, which means that the output of the two 9516 chips is either delayed by 14 cycles or 15 cycles. Then the output signals should be aligned with "input to CLK". Of course, this is my personal simple idea. In fact, I'm not sure that this idea is right. I just want to try and make sure.
Maybe the CLK signal is not aligned at the input of ad9516. However, since "output of channel divider" is aligned with "input to CLK", as shown in the following figure. Then the output between two ad9516 blocks should not exceed the period of one input CLK at most(as shown in the red circle in the following diagram). However, my simple experiment shows that there are many kinds of output. I repeated experiments, the current state is that there are at most four clock cycles between two ad9154 chips. This is what I don't understand.
4.Thank you again for your advice. I have a general idea of your sketch. But what do you mean by "because the out8 / out9 clock flows" unobstructed "into the bottom ad9516, all outputs from both chips will be synchronized"? If we do experiments according to this diagram, two pieces of ad9516 are equivalent to a series structure. Why is it possible to align all outputs? I didn't see this information in the datasheet. At the same time, if I use this architecture, I need to redesign the PCB board. This generally takes a long time.
Thank you very much.
I took two AD9516 evaluation boards. I took an AD9545 eval board and I created two separate 250 MHz outputs that are in phase. I supplied these two clocks to the AD9516 eval boards at CLK connector. This replicates your configuration. Then I programmed the AD9516s to take CLK and provide it at OUT0 (set as 250 MHz 780 mV LVPECL).
Please note I bypassed the Divider 0, so it does not influence at all the data path.
I then captured on the oscilloscope the OUT0 clocks of both AD9516 board:
Channel 1 (yellow) is the input clock sensed at another AD9545 board output.
Channel 2 (green) and Channel 3 (blue) are the output clocks of the AD9516s at OUT0 connectors.
Please note that the connections between the boards and the oscilloscope are done with cables of same length. The connections between the AD9545 board and the AD9516 boards are also done with equal length cables.
There is a delay between the Channel 1 clock and the Channels 2 and 3 clocks because these last two clocks have a longer path from the AD9545 board to the oscilloscope.
But the important thing is the Channel 2 and 3 are in phase, showing the AD9516 outputs are aligned.
I then pressed the SYNC buttons S5 on each AD9516 board one at a time (executing a synchronization operation on that particular AD9516) and every time the Channel 2 and 3 clocks showed up aligned. This happens because I bypassed the channel dividers and therefore there is nothing to sync.
The CLK input is buffered to the outputs and the outputs of both chips are always aligned.
Bottom line: I was wrong yesterday when I pointed to that phrase in the data sheet. Bypass the dividers and this will allow the outputs to always by aligned to the input.
Regarding my alternative approach: When you first synchronize the bottom AD9516, there is no clock coming in. Then you synchronize the top AD9516. The chip begins to provide outputs and two of these outputs go to the bottom AD9516, pass through it and are distributed to its outputs. They are unobstructed and therefore aligned o the inputs, that is to the outputs of top AD9516.