I recently started gathering information for a new project. I need to have a pulsed trigger signal transmitted to 10 ICs with very small jitter.
For example 100 pulses with 10ns length and 50 ns gaps in between. And that pattern is repeated with 1Hz.
The problem I found is that many clock fanout datasheets specify a duty around 50%. In the FAQ is stated:On the AD9510, how can I make sure that the duty cycle of output clocks stays within 40% to 60% duty cycle window?A divide-by-3 will produce a duty cycle of 33.3%-66.6%. A divide-by-5 produces exactly 40%-60%. Higher odd divide ratios (7, 9, 11...) produce duty cycles within the 40%-60% window.
My question is whether the ADCLK950 can work with arbitrary pulse patterns as in my example?
If this works I would like to use the LTC6957-3 to get back to CMOS voltage levels. Do you see any problems there?
Thanks in advance
please tell me what is the duty cycle of the 100 clocks you create.
The AD9510 dividers block ensures the clock outputs have the desired duty cycle (the one you program into the configuration registers). If you want to replicate the duty cycle of the input clock (the one received at CLK1 pins), just bypass the dividers.
The ADCLK950 fans out whatever clock (including its duty cycle) is received at CLK0 or CLK1 pins.
I would suggest to look also at the ADCLK846. It has 6 differential outputs that can be set as 12 CMOS ones and it also fans out clocks, which means it replicates the duty cycle of the input clock.
I just realized that I mixed up the AD9510 and the ADCLK950. I went to the FAQ page of the ADCLK950 and there I read the statement about the AD9510. My bad.
The signal I want to transmit is basically an arbitrary digital signal. It is not possible to specify a duty cycle. I depends on the user and could be 5ns pulses with a 10Hz repetition rate. The ADCLK950 can do that, right?
The reason for using the ADCLK950 is that I need a very precise signal with low jitter. The distance between the ADCLK950 and the receiving ends is probably 0.5m. This led me to the conclusion that a terminated transmission line is necessary. And due to a considerable amount of noise in the vicinity I chose LVPECL.
To trigger the device I need at least 2.6V which brought my to the LTC6957-3. I would place the LTC6957-3 directly in front of the target MOSFET driver.
The ADCLK846 CMOS outputs are specified with 250 MHz for CMOS which isn´t as fast as I want it to be and unterminated transmission lines aren´t an option.
Thank you for your answer, if you see any problems with my idea please let me know.
The ADCLK950 can fan out 5 ns (200 MHz) pulses. Just be aware that the chip introduces a delay (see Propagation delay entry in Table 2, page 3, rev B data sheet) and there is an output to output skew.
Use differential outputs to transmit into LTC6957-3. I see this chip can accept differential LVPECL inputs, so it should work.