Using the ADCLK950 for a pulsed application / random pulse patterns.

Hello everybody,

I recently started gathering information for a new project. I need to have a pulsed trigger signal transmitted to 10 ICs with very small jitter.

For example 100 pulses with 10ns length and 50 ns gaps in between. And that pattern is repeated with 1Hz.

The problem I found is that many clock fanout datasheets specify a duty around 50%.
In the FAQ is stated:
On the AD9510, how can I make sure that the duty cycle of output clocks stays within 40% to 60% duty cycle window?
A divide-by-3 will produce a duty cycle of 33.3%-66.6%. A divide-by-5 produces exactly 40%-60%. Higher odd divide ratios (7, 9, 11...) produce duty cycles within the 40%-60% window.

My question is whether the ADCLK950 can work with arbitrary pulse patterns as in my example?

If this works I would like to use the LTC6957-3 to get back to CMOS voltage levels. Do you see any problems there?

Thanks in advance