configured chip HMC7044 at cmos output mode.
It is working but I have some problems:
HMC7044 have 2 group
Group1: 3 clk + 4 SCLK same phase: CLK0, SCLK3, SCLK5, CLK6, SCLK9, CLK10, SCLK13.
Group2: 4 CLK + 3 SCLK same phase: other.
But group 1 and group 2 reverse phase.(same datasheet page 33)
I want group 1 and group 2 same phase, I used to multislip delay after sync, result group 1 same phase with group 2.
Now, I have questions:
Q1: Why output cmos mode HMC7044 have 2 group?
Q2: What is problem if I use multislip for group 1 and group 2 same phase?
Q3: If I use 4 CLK + 3 SCLK(group 2) work as clock with frequency < 300MHz.
What are differences between CLK and SCLK when HMC7044 at clock output mode? When SCLK work as clock, what is the quality assurance?
As it is given in the datasheet and you stated, additional slip must be used for Channel 0, Channel 3, Channel 5, Channel 6, Channel 9, Channel 10, and Channel 13 if output driver is selected as CMOS. This additional slip does not cause performance degradation. You can safely use slip for phase synchronization of CMOS outputs.
All channels of HMC7044 are identical, CLK and SCLK are just naming. You can set each channel either device clock or SYSREF clock, separately. There is also no problem with any channel for <300 MHz operation.