I'm using HMC7043 for JESD204B system to generate clocks and SYSREF signals.
I need to use SCLKOUT channel for the core clock to JESD IP in FPGA.
Here is my question.
The datasheet of HMC7043 says that SCLKOUT channel is "default SYSREF profile".
What is the difference between DLK profile and SYSREF profile?
HMC7043 has default register settings on power-up. CLKOUTx channels are continuous clock outputs and SLCKOUTx channels are SYSREF channels by default.
CLKOUTx and SCLKOUTx is just naming actually. All 14 channels are identical and each channel can be configured as continuous device clock, continuous SYSREF clock or pulsed SYSREF clock, individually.
Thank you for reply.
It is helpful.