Hello,I have some questions about using AD9520 PLL.
I make a board of AD9520-3 .The REFCLK is 25MHz.The configuration of the PLLare shown below: R=100; N=8000; charge pump is 4.8mA.I design the PLL loop filter by ADIsimCLK as so:
I want the output signal is 2GHz,so I route VCO divider input directly to the outputs.Then I have somesquestions as follow:
1 The frequency of outout is 2.450GHz,after the VCO calibration.But without the VCO calibration,The frequency of outout is 2GHz.
2 When the frequency of output is 2GHz,the PLL isnot locked.The pin CP is always 5V, the pin LF is always 3.7V,which are greater than the maximum data in the datasheet.I detect the signal on the pin STATUS.When the 0x017[7:2]=000010,I can see the R divider output.When the 0x017[7:2]=000001,0x017[7:2]=000011,
0x017[7:2]=000100,0x017[7:2]=000101,0x017[7:2]=000110 and 0x017[7:2]=101011,the pin all do not have any signal.So I donot know the condition of the on-chip VCO.
There are some errors in my operation maybe,I am pleased for your suggest.