I translated your inquiry, and this is what I get:
In my design, the reference clock used by the AD9548 is from OCXO with a frequency of 10MHz;
According to the requirements of the manual, the FPGA is used to configure the AD9548's registers through the SPI. When reading back the registers, such as the clock cycle (0x0103 ~ 0x0108), the values are correct, but reading back the value of the 0x0D01 register is basically 0x00 and occasionally 0x10 This phenomenon should be abnormal;
Is there anything in the register configuration process that requires special attention?If there are things in the register processThe special consideration for register 0x0D00 and register 0x0D01 is that they require an IO_UPDATE. (Register 0x0005 = 0x01) in order to reflect their latest status.Best RegardsLouijie
I have moved this thread to Clock and Timing forum.
the register 0xD01 is a status register, so its bits may vary. For example, the bit 4 that you see sometimes being equal to 1 means the system clock is stable. It should be always 1.
Please send me the OCXO data sheet and the schematic you use for it, so I can take a look.
Also, please send me the registers values you use to configure the chip. If you used the evaluation software to obtain the configuration, please send me the setup file you can save from it.