I recently used daq2(with own verilog), but there was a problem configuring ad9523-1 through spi that pll2 is not locked. the value of 0x22c is 'a0' the value of 0x22d is '09'.
now，i have some questions to ask.
1. i will paste my configuration datesheet table.
2. what is the right value of register of '0x22c' and '0x22d'
3. Is there any delay process during register configuration,because i write the register step by step with 10M clock
4. what influence can hlodover is active make?
reg adrr value
the fact that register 0x22C is 0xA0 tells you the REFA, REFB are missing. So you need to make sure you provide the right reference clock(s), that is they meet the specification.
Because the reference clock(s) were missing, the PLL1 enters holdover. This is why bit 3 of register 0x22D is 1.
You say bit 0 of register 0x22D is 1, which means the VCO calibration of PLL2 is in progress. This bit should go to 0 after a certain amount of time.
Read back the register you write to ensure you write them correctly.
Use IO Update operation to transfer the data you write into registers into the actual control registers. See this at page 33 in the data sheet:
what's more, I still don't know how to make the pll2 locked.
I'm not an expert in fmcdaq2. Maybe you should post this on the group that supports this board.
I can only respond to your questions strictly about AD953-1.
If REFA and REFB are not used, you can power down their receivers: bits 3 and 4 in register 0x1A cleared to 0.
Regarding the bit 1 (Calibrate VCO) in register 0xF3. You set it to 1 to start the VCO calibration. Then you poll bit 0 in registerr 0x22D (VCO caliubration in progress). It should be 1 during calibration. Then it should clear to 0 to state the calibration has ended. Then you write 0 to bit 1 in register 0xF3 to stop the calibration process.
oh，I've been obsessed with this question for a very long time. the pll2 was not locked.
I used an oscilloscope to measure the output of a channel. Although there was a waveform, its clock frequency was wrong. the 22c is a0; the 22d is 09;
can you help me to make the pll2 locked. my configuration data is pasted in data sheet.
this picture is the schematic of ad9523-1.The link is completehttps://wiki.analog.com/_media/resources/eval/user-guides/ad-fmcdaq2-ebz/fmcdaq2_reve.pdf
I loaded the register values you sent earlier into an AD9523-1 evaluation software
REFA and REFB are in power down.
PLL1 is in tristate.
From the schematic the external VCXO is 125 MHz. The PLL2 seems to be configured correctly. I cannot verify it on an evaluation board because the VCXO is 122.88 MHz.
From the log you sent, I do not see the VCO calibration operation as I described to you in my previous email. In my view, if you do that, it should provide at OUT6 (the only output enabled) 7.8125 MHz. Make sure you put a 100 ohm resistor as load because on the fmcdaq2 schematic I saw only the ac coupled capacitors
thank you very much
i follow your advice that when the calibration has ended, write 0 to bit 1 in register 0xF3 to stop the calibration process. the 0x22c is 'a2'. the 0x22d is '08'. the pll2 is locked.
I know that if not to write 0 to bit 1 in register 0xf3，the pll2 is not locked. although the output is right , stop calibration is necessary.