the ad9523-1 pll2 not locking

I recently used daq2(with own verilog), but there was a problem configuring ad9523-1 through spi that pll2 is not locked. the value of 0x22c is 'a0' the value of 0x22d is '09'.

now,i have some questions to ask. 

1. i will paste my configuration datesheet table.

2. what is the right value of register of '0x22c' and '0x22d'

3. Is there any delay process during register configuration,because i write the register step by step with 10M clock

4. what influence can hlodover is active make?

reg adrr      value
0000          24;              
0004          01;
0234          01;
0011          00;
0010          01;
0013          00;
0012          01;
0017          00;
0016          01;
0019          00;
0018          80;
001A          05;
001B          60;
001C          84;
001D          01;
00F0          76;
00F1          06;
00F2          13;
00F3          02;
00F4          40;
00F7          01;
00F5          3A;
00F6          00;
01A2          01;
01A3          7F;
01A4          04;
0233          00;
0230          02;
0231          03;
0232          00;
0234          01;
0232          01;
0234          01;
0232          00;
0234          01;

  • HI,

    the fact that register 0x22C is 0xA0 tells you the REFA, REFB are missing. So you need to make sure you provide the right reference clock(s), that is they meet the specification.

    Because the reference clock(s) were missing, the PLL1 enters holdover. This is why bit 3 of register 0x22D is 1.

    You say bit 0 of register 0x22D is 1, which means the VCO calibration of PLL2 is in progress. This bit should go to 0 after a certain amount of time.

    Read back the register you write to ensure you write them correctly.

    Use IO Update operation to transfer the data you write into registers into the actual control registers. See this at page 33 in the data sheet:

    Petre

  • hi, thanks your reply.

    after reading your reply ,i'd like to ask you a few questions.

    Firstly,i'm using the fmcdaq2, the ad9523-1 is a part of fmcdaq2.It's the key.  In the ADI's design of fmcdaq2, the REFA and REFB is not used .so ,what did i do about REFA and REFB. the reference clock is from osc_in.

    secondly,   i know set calibration bit (bit 1 of 0x0f3)  to 1 can start calibration,but don't know Do i need to manually set this bit (bit 1 of 0x0f3) to 0. And ,if needed, when i should set this bit to 0.

  • what's more, I still don't know how to make the pll2 locked.

  • HI,

    I'm not an expert in fmcdaq2. Maybe you should post this on the group that supports this board.

    I can only respond to your questions strictly about AD953-1.

    If REFA and REFB are not used, you can power down their receivers: bits 3 and 4 in register 0x1A  cleared to 0.

    Regarding the bit 1 (Calibrate VCO) in register 0xF3. You set it to 1 to start the VCO calibration. Then you poll bit 0 in registerr 0x22D (VCO caliubration in progress). It should be 1 during calibration. Then it should clear to 0 to state the calibration has ended. Then you write 0 to bit 1 in register 0xF3 to stop the calibration process.

    Petre

  • oh,I've been obsessed with this question for a very long time. the pll2 was not locked. 

    I used an oscilloscope to measure the output of a channel. Although there was a waveform, its clock frequency was wrong.  the 22c is a0; the 22d is 09;

    can you help me  to make the pll2 locked. my configuration data is pasted in data sheet.

    this picture is the schematic of ad9523-1.The link is completehttps://wiki.analog.com/_media/resources/eval/user-guides/ad-fmcdaq2-ebz/fmcdaq2_reve.pdf