How to achieve synchronization between two ad9576 to ensure that all 16 ad output clock phases are synchronized?

My system now needs to use two ad9576 to drive 16 ad9265 100MHz / CH samples, each ad9576 drives 8 100MHz AD sampling clocks, 16 AD sampling clocks need to realize phase synchronization, one ad9576 can realize phase synchronization between 0-8 output clocks, then how can two ad9576 realize synchronization to ensure that 16 ad output clocks are synchronized?

  • 0
    •  Analog Employees 
    on Dec 18, 2019 4:23 PM


    I assumed you chose the AD9576 to do this because it accepts a crystal resonator as a reference clock. Yes, you can synchronize two AD9576s to produce all 22 outputs at 100 MHz synchronized. Please note that the alignment of the outputs is not exactly 0. The data sheet lists the skew between outputs in Table 9, page 10, AD9576 revA data sheet.

    Then there is the zero delay timing between the reference and the outputs, which is several ns. See Table 9.

    Other alternatives to this approach:

    - you can obtain 100 MHz with one AD9576 and then use one ADCLK854s fan out buffer in CMOS output mode to obtain the 20 synchronized clocks.

    - you can use an AD9528 instead of the AD9576 if you need better phase noise performance, but you need to create a reference clock and use an external VCXO.

    - do you have a reference frequency created by a different chip that you can use as a reference to AD9576? This would allow you to use only PLL0 of the AD9576 to produce the 100 MHz and then use iot with the ADCLK854 like above.

    Below I present how to synchronize two AD9576s, to respond to your question.

    Let’s talk first about synchronizing all outputs of one AD9576. You can set PLL0 to provide an output to all OUT0 to OUT9 and configure them to be all aligned at 100 MHz.

    OUT10 comes only from PLL1 and therefore we need to find a way to synchronize OUT10 to the other outputs.

    This means to have PLL0 and PLL1 have the same reference, which is possible: let’s chose REF0=25 MHz. We have to chose 25 MHz because this is the typical reference frequency of PLL1.

    Then we need to have the PLLs work in an equivalent “zero delay” mode, that is their outputs right before the distribution dividers to match the PFD frequency. We can close the PLL0 loop to include M0.

    This is the configuration of the AD9576 to provide all OUT0 to OUT10 synchronized.

    As a procedure, provide the reference, lock the PLLs and then provide the SYNC command to generate the outputs.

    Now, to synchronize two AD9576s, you have two choices:

    • one is to take the 25 MHz used at REF0 of the 1st AD9576 and provide it at the REF0 of the second, configure the second as the first and sync both chips in the same time
    • the other (if for example the 25 MHz at REF0 was from a crystal) is to take 100 MHz from one of the 1st AD9576 outputs and provide it at REF0 of the 2nd AD9576. Then set PLL0 of the 2nd AD9576 to lock onto this 100 Hz in “zero delay” mode as in the figure below. PLL1 cannot be used because its PFD cannot accept 100 MHz input, so the second AD9576 OUT10 must replicate REF0.