We are using LTC6951 to generate dev clock and sysref.
Input reference Frequency is 30.72Mhz .First three outputs are configured for 122.88Mhz output frequency and last two outputs are configured for 3.84Mhz frequency.
Phase difference between first four outputs are in the rage of few nano seconds.
Phase Delay of 70ns is observed between last two outputs. Configuring delays between last two outputs is not helping to correct phase difference.
Please find the attached register set configured.
# All values in Hexadecimal
# Register values from 0x00 to 0x13:
0x00, 0xba, 0x00, 0x78, 0x83, 0x04, 0xa0, 0x07, 0x20, 0x95, 0x00, 0x95, 0x00, 0x95, 0x00, 0x9f, 0x00, 0x9f, 0x00, 0x00
# Addr Value
Suggestions would be helpful.
You register settings look correct. What you are describing sounds like the output dividers have been programmed, but not synchronized. Have you performed the SYNC operation? This can be done by toggling the SYNC pin or the SSYNC register bit. The sync signal will need to remain high for 1ms. There is some discussion about this in the datasheet.