LTC6951 clock output phase issue

Hi ,

We are using LTC6951 to generate dev clock and sysref.

Input reference Frequency is 30.72Mhz .First three outputs are configured for 122.88Mhz output frequency and last two outputs are configured for 3.84Mhz frequency.

Phase difference between first four outputs are in the rage of few nano seconds.

Phase Delay of 70ns is observed between last two outputs. Configuring  delays between last two  outputs is not helping to correct phase difference.

Please find the attached register set configured.

# All values in Hexadecimal
# Register values from 0x00 to 0x13:
0x00, 0xba, 0x00, 0x78, 0x83, 0x04, 0xa0, 0x07, 0x20, 0x95, 0x00, 0x95, 0x00, 0x95, 0x00, 0x9f, 0x00, 0x9f, 0x00, 0x00

# Addr 	Value
0x00 	0x00
0x01 	0xba
0x02 	0x00
0x03 	0x78
0x04 	0x83
0x05 	0x04
0x06 	0xa0
0x07 	0x07
0x08 	0x20
0x09 	0x95
0x0a 	0x00
0x0b 	0x95
0x0c 	0x00
0x0d 	0x95
0x0e 	0x00
0x0f 	0x9f
0x10 	0x00
0x11 	0x9f
0x12 	0x00
0x13 	0x00

Suggestions would be helpful.



  • 0
    •  Analog Employees 
    on Dec 16, 2019 3:24 PM

    Hi Sandeep,

    You register settings look correct.  What you are describing sounds like the output dividers have been programmed, but not synchronized.  Have you performed the SYNC operation?  This can be done by toggling the SYNC pin or the SSYNC register bit.  The sync signal will need to remain high for 1ms.  There is some discussion about this in the datasheet.