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Regarding the 9520-4, I want to use the 9520 to lock a signal at a far end of about 40Mhz, and come out to generate phase-dependent signals of 160M and 40M. The following figure is the design generated by ADIsimCLK software. Some questions are not clear:
1. If the frequency of VCO is set to 1.6Ghz, Vcp = 5V, Icp = 4.8ma. Kvco = 35Mhz / V. In this case, is the frequency from the VCO only greater than 1.6Ghz? From 1.6G to 1.6G + 35M * 5 = 1.775Ghz, the frequency range after 40 frequency division is 40M ~ 44.375Mhz. Can't the far-end frequency exceed this range?
2. If the far-end signal range is 38M ~ 42M, should I reduce the VCO frequency to 1.52Ghz?
3. At the beginning of power-on, when there is no input signal, will the VCO output a 1.6Ghz signal or an indefinite frequency signal? thank you

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• Hi,

It is good you set VCO frequency at 1.6 GHz because you can divide it down to obtain the 160 MHz and 40 MHz that you target.

When you configure the chip, you download the configuration and then calibrate the VCO. It will be spot on 1.6GHz.

The Kvco is the VCO constant. You do not need to care about it. Just make sure the PLL dividers and the charge pump are configured at the values you used in the ADIsimCLK.

If there is no reference, the PLL enters holdover mode. See the section in the rev B data sheet at page 39.

Petre

• thanks very much。

my design：The center frequency of the input signal is 40Mhz, and I want to track the frequency and phase changes with the 9520. i Want to know the maximum frequency range of an input signal when VCO is1.6Ghz?

And is the phase detector of the 9520 as shown below? Input signal does not require 50% duty cycle

• Hi,

Please use the data sheet for these kind of questions.

Table 2 at page 4 states clearly the reference clock can be up to 250 MHz, so you can use 40 MHz reference clock.

The VCO can have any frequency between 1.4 GHz and 1.8 GHz (another entry in the Table 2), so you can configure a PLL with a VCO frequency being multiple of 40 MHz within this range.

I do not know the schematic of the PFD inside the AD9520, but make sure the PFD input frequency is lower than 100 MHz (page 5)

Petre

• Hello, let me make my question clearer. My input signal is about 40M, maybe 41M or 39M, and I don't know the exact frequency. I just want to Frequency and phase synchronization. So I have set the frequency of the VCO to 1.6G and other parameters have been set. I want to know the range of the input frequency, beyond this range, such as 38M, can not be locked at this time, because the voltage of the VCO is out of range, or for some other reason. I can't change the settings of the 9520 at will. Thank you

• Hi,

when the reference frequency varies around 40 MHz, the PLL tries to keep the lock. The charge pump tries to adjust the output current to change the VCO to keep the lock. If the charge pump current reaches its limit (which is programmable between 0.6 mA to 4.8 mA), then the PLL looses the lock.

If the reference clock does not maintain its frequency and it varies, it may well happen the VCO reaches its limit as well and the PLL looses lock. The data sheet states at page 35 that "once the VCO is calibrated, the vCO has sufficient operating range to stay locked over temperature and voltage extremes without needing additional calibration", but this supposes the reference frequency remains constant.

The AD9520-4 has some status monitors of the VCO and of the references (see Table 17, page 15). You can use them to monitor the VCO and the references.

Petre