AD9520 PLL frequency question

Regarding the 9520-4, I want to use the 9520 to lock a signal at a far end of about 40Mhz, and come out to generate phase-dependent signals of 160M and 40M. The following figure is the design generated by ADIsimCLK software. Some questions are not clear:
1. If the frequency of VCO is set to 1.6Ghz, Vcp = 5V, Icp = 4.8ma. Kvco = 35Mhz / V. In this case, is the frequency from the VCO only greater than 1.6Ghz? From 1.6G to 1.6G + 35M * 5 = 1.775Ghz, the frequency range after 40 frequency division is 40M ~ 44.375Mhz. Can't the far-end frequency exceed this range?
2. If the far-end signal range is 38M ~ 42M, should I reduce the VCO frequency to 1.52Ghz?
3. At the beginning of power-on, when there is no input signal, will the VCO output a 1.6Ghz signal or an indefinite frequency signal? thank you