I'm currently trying to get phase lock between my 1PPS signal and 1Hz output 0A. I have a 100MHz output at Out0A, and my external clock source is 50MHz square wave. My loop bandwidth is currently set to 20 mHz. My phase/freq drain/fill rate is set to 200. Timeout duration is 1ms and lock settle time is 10ms (I've tried it with 50s and 10s, but didn't seem to get a lock either). Phase lock threshold is at 2000.
My reference input and clock are both valid. There is frequency lock detection, just no phase lock. The PLD light will flicker on for one second, then turn off again for 3-5 seconds, I can't seem to get a better lock than that.
What other parameters/registers can I change to get a solid phase lock between the 1PPS and 1Hz output?
1Hz output at Out0B*
I believe the problem is the external clock source is not stable enough and this gets you in and out of phase lock.
Try using the crystal resonator as the system clock source and use an additional stable external reference source to compensate the system clock. Setting this in the evaluation software:
It practically uses the method 3 described in the rev B AD9545 data sheet at page 142: