Hi,
I am working on the AD9822 CCD signal processor in bench and verifying its functionality in 1-channel CDS mode.
I have set the offset voltage to be 3V by configuring the resister.
My input signal is CCD waveform with reference level at 2V and data level at 1V at 1MHz frequency.
The clocks (ADCCLK,CDSCLK1 & CDSCLK2) are also operated in 1MHz frequency.Timing and levels are checked and followed as per the datasheet spec.
I am observing the output code to have random drop to 0V.(Image shown below)
The plot is number of samples vs the output code (in terms of voltage)
As the number of input CDSCLK1 cycles given is increased then the output samples drop to 0V also increases.
The drops to 0V are occuring shortly.
The hardware setup is as per the application diagram of datasheet.
Please help me to solve the issue.
Thanks