ADRV9009 VCXO change causes Error 173 Clock PLL Lock Event timeout

Hello,

Starting from a fully working ADRV9009-based system, we modified the ADRV9009 eval board to test out a change we plan to make on our custom HW.  We replaced the 122.88 MHz VCXO with a 120 MHz VCXO.  And the 30.72 MHz RefClk input to the ADRV9009 has been replaced with a 10 MHz RefClk.  My custom profile looks like this:

This profile was imported into TES, with these config settings:

And TES was then used to generate the Init.c files.  The new profile resulted in only 2 changes:

(1)  In file talise_config_ad9528.h :  the 7th param (vcxo_Frequency_Hz) was updated to 30720000:

static ad9528pll1Settings_t clockPll1Settings =
{
    30720000,
    1,
    3,
    0,
    1,
    0,
    30720000,      <----   previously was 122880000
    2,
    4
};

(2) In file talise_config.c :  in the talInit struct, the deviceClock_kHz setting was updated to 30720 :

    /* Digital Clock Settings */
    .clocks =
    {
        .deviceClock_kHz = 30720,            /* CLKPLL and device reference clock frequency in kHz */     <----  previously was 122880
        .clkPllVcoFreq_kHz = 9830400,        /* CLKPLL VCO frequency in kHz */
        .clkPllHsDiv = TAL_HSDIV_2P5,            /* CLKPLL high speed clock divider */
        .rfPllUseExternalLo = 0,                /* 1= Use external LO for RF PLL, 0 = use internal LO generation for RF PLL */
        .rfPllPhaseSyncMode = TAL_RFPLLMCS_NOSYNC                /* RFPLL MCS (Phase sync) mode */
    },

These 2 lines are the only changes in my custom config.  When I run the code I get the following error:


      ERROR: 173: Clock PLL Lock event timed out in TALISE_waitForEvent()
      error: TALISE_initialize() failed

This error is generated in talise.c line 842, waiting for event TAL_CLKPLL_LOCK :

       retVal = (talRecoveryActions_t)TALISE_waitForEvent(device, TAL_CLKPLL_LOCK,
                                                                                                      CLKPLL_LOCK_TIMEOUT_US, CLKPLL_LOCK_INTERVAL_US);

       IF_ERR_RETURN_U32(retVal);

I measured the VCXO frequency (= 120 MHz), and measured the RefClk input  (=10 MHz).  Can you help me determine why the PLL is not locking with this custom configuration?

Thank you,

Keith