I am working on a system that requires a 32.768MHz master clock delivered to 5 separate locations (single-ended CMOS). The system also needs to take a 1PPS signal from GPS receiver as an input to synchronize.
I do not see any readily available TCXO or OCXO oscillators with that precise frequency.
Therefore, my question is this: does AD9544 support five 32.768MHz outputs from a 20MHz OCXO oscillator (most commonly available freq. OCXO >=20MHz on digikey right now) system input and a 1PPS reference input?
The 1PPS signal may or may not always be present, hence the OCXO for quality system input in case 1PPS signal not present.
Yes, the AD9544 will accomplish this task. You can use the 20MHz OCXO as the System Clock input and the 1PPS as a reference input. When the 1PPS goes away, the device will enter holdover and the outputs will continue with the stability of the System Clock OCXO. This may be adequate for your application. However there is a significant degradation (>6dB) in phase noise by using such a low frequency system clock. If phase noise is a concern (see datasheet graphs), then a better approach is to use a 52MHz Xtal on the System Clock with the internal System Clock frequency doubler enabled. The 20MHz OCXO is then a reference input like the 1PPS. The AD9444 can use the OCXO to stabilize the 52MHz Xtal to allow the low loop bandwidth (<50mHz) required for 1PPS operation. This will give excellent stability and phase noise performance. (We no longer recommend using the System Clock frequency doubler with an OCXO.)
The AD9444 datasheet will be updated soon. For more detailed operation of the AD9444, use the updated AD9545 datasheet with the understanding that he AD9444 has identical performance except that it does not support Auxiliary NCOs, Auxiliary TDCs, and Embedded Clock Modulation/Demodulation found in the AD9545.
To further clarify the situation:
I need to have external 1PPS signal input as well as 1PPS signal from processor (ultimately derived from PTP ethernet timing). Only one of these 1PPS signal sources would be used at a time.
Questions about this configuration
Does ADI have any comments on these questions?
I apologize for the delay. Responses to your questions are given below:
1) The stable oscillator (OCXO or TCXO) stabilizes the System Clock through System Clock Compensation (see System Clock Compensation p.137 Rev B AD9545 datasheet with focus on Closed-Loop Method and Compensation Method 3). This compensation removes the effects of the 52MHz Xtal's wander and allows the required 50mHz DPLL loop bandwidth for a 1PPS reference input.
You are correct that each DPLL can only have 1 active reference at a time. However, the stable oscillator is used to drive the AuxDPLL which compensates the System Clock and consequently the DPLLs for any reference input.
2) The OCXO/TCXO will stabilize the 52MHz Xtal when no 1PPS is present. The device will switch to holdover and benefit from the stability of the OCXO/TCXO. However, as noted in #1 above, you need to run a low loop bandwidth with a 1PPS input for loop stability. Therefore the stable reference also has a role when either of the 1PPS signals are present.
Based on your earlier system description of two 1PPS signals, you will probably want to setup 1 DPLL profile that uses the primary 1PPS and one profile that uses the secondary 1PPS. These profiles can either be revertive or not.
Thanks very much, that definitely helps my understanding.
Can you please take a look at the attached schematic snippet and provide any comments/feedback?
CLKOUT1_1V8 and TIMER16_1V8 are clock signals from my main processor (one, a general clock output, the timer one will be the 1PPS output from processor). Both of these signals are level shifted thru SN74LVC1G125, similar to the External 1PPS signal, shown in this snippet.
Also, I have used AC-coupled inputs to SN74LVC244A to level-translate the clock outputs from 1.8V to 3.3V signal level, please let me know if this isn't an advisable way to operate.
I am expecting all five outputs to be running at 32.768MHz, ultimately.
Does ADI have any comments on this schematic snippet?
Feedback on schematic:
1) I have some concerns about the output terminations. I can see that the 10K resistors should setup the common mode for the signal at 3.3V/2. This seems high. I'm assuming that you will adjust the resisters to restore the proper common mode and slew rate at the level translator. For compatibility see the AD9545 datasheet Rev B pages 46 & 47. The AD9544/45's output drivers are current sources/sinks depending on how they are programmed.
2) The 10K pulldown on ResetB will hold the part in reset unless pulled up elsewhere. The device has an internal 100K pull up.
3) You have configured the device for I2C operation at startup. You may want to have a test point for all of the MPINs. This can be valuable in debug mode to program the MPIN's as status pins to observe internal operation of the device. Of course, this can also be accomplished with IRQ's and by reading the status registers.