LVDS and LVCMOS output clock in phase

Hello all

I was looking for a "simple" PLL that can generate two clocks, a fast one (eg: 480MHz) and a slow one (eg: 48 MHz) with a known and fixed phase between each other. Ideally the phase is 0. But in any case, I can't find very accurate phase relation documentation in the datasheets. The fast one should be LVDS and the slow one an LVCMOS (3.3V). I am worried about a different delay between the two output buffer types but even then this information is not in the datasheets so I can't know for sure until I measured it or if someone shares their experiences.

The PLL that seems easy to configure is for instance AD9550, but any suggestion to look elsewhere to a different product is also appreciated if some part is more appropriate for my application.

Thanks for your support

Gerrit

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