We have successfuly used tree of HMC704x chips for clock distribution of desired frequencies.
Now we are facing problem with simple distribution of the ultra low noise 125MHz clock where the HMC7044 (1st stage of the clock tree) is in distributed mode (FIN input as external VCO).
We observe degradation in phase noise of output clocks for frequency offsets to 10kHz when compared to input clock phase noise from 10Hz to 10kHz. These low offsets are actually very critical for our ultra-narrow band application. I have reproduced it with eval kit HMC7043 to exclude an error in our design.
I believe it is related to FIN input limitation of HMC704x. I don't see any specifications for FIN input in HMC7044's datasheet but the HMC7043's datasheet specifies CLKIN lower limit 200 MHz.
I know you have LTC6953 as alternative to HMC704x solutions. Could it be usable for our requirements or can you please recommend a replacement for HMC704x solution which is JESD204 compliant?
Thanks and regards,