Clock distribution of ultra low noise OCXO

Hi Daniel,

Can you clarify a few things for me?  Are you seeing this phase noise degradation after one HMC7043 or after multiple stages of the HMC7043.  Also what are your 125MHz clock signal characteristics - amplitude, waveform type and if its a square wave what is its slew rate?  What phase noise targets do you need to achieve in the 10Hz to 10kHZ range?  Do you have a phase noise plot of the OCXO and the HMC7043 outputs?

The reason I'm asking is for a couple reasons.  One reason is to rule out AM-PM conversion with whatever circuit we recommend. I'm assuming if its an OCXO it probably has a 10dBm to 13dBm sinewave output.  For 125MHz the slew rate isn't terrible fast (maybe 1GV/s = 1V/ns). 

the following plot is from the LTC6953 datasheet.

This app note discuss this some also (https://www.analog.com/media/en/reference-design-documentation/design-notes/dn514f.pdf)

Hi Chris,

We have only one stage of HMC7043. It is actually one main HMC7044 (stage 1) and four HMC7043 (stage 2).

The OCXO has sinus output, circa 500mV, load 50 ohm.

The phase noise should be or better:

10Hz @ <-95dBc/Hz

100Hz @ <-127dBc/Hz

1kHz @ <-153dBc/Hz

10kHz @ <-160dBc/Hz

...

I will upload measurements when I will get back the board with OCXO - it has buffered output from LTC6957 as option.

I´m afraid that we will have to design a solution where used ADcs are clocked directly. The HMC704x will be used for JESD reference clock and SYSREF generation.

Thanks and regards,

Daniel

500mV peak to peak or 500mv pk?  I can try some measurements here with a few different parts and a 100M OCXO. 

What phase noise analyzer are you using?  Just trying to mimic your setup.  The 125M numbers are sometimes limited by the test instrument also.  Discussed here.

https://ez.analog.com/clock_and_timing/f/q-a/101357/ltc695x-low-frequency-phase-noise-measurement-issues/301260#301260

We do have a LTC6953 datasheet plot with a 100M OCXO at different input amplitude levels.   We had to use the method in the above link to beat the instrument induced errors to get that plot.

>500mVpp (or LTC6957 output).

I would like to repeat a measurement with R&S FSUP50 but I have prepare all components. For tentative measurement we have R&S FSW with OCXO options but it is useless for this purpose with its phase noise sensitivity.

Right now I use different approach where I evaluate clock phase noise from output of ADC through ultra-narrow band DSP. This is described in your AN-756. My whole problem is about "skirted shape of clock signal" convolved on converted strong signals - near weak desired signals are drowned because of lower NSD in the filtered narrow band.

If you can do some measurements I would really appreciate it! HMC7043 doesn't seem usable because of its  additive phase noise and 1/f noise for <200MHz clocks.

Regarding LTC6953 plot.

I'm not sure what IN+- pins trace means.

IN+/- Pins refers to the phase noise of OCXO at the LTC6953 input pins (which are labeled IN+/-).  

In regards to the HMC7043.  I have ordered a board.  It has not arrived yet.  However, I'm wondering if your close in noise is dominated by your power supply?  What power supply are you using?  I've been cleaning up my power supplies with the LT3042 or LT3045 recently.  

I've looked at the LTC6957-1 today.  Which version of the LTC6957 do you have on your board?

Based on today's results I'm not too worried about the 10Hz to 1kHz specs you provided above.  The 10kHz numbers will require some more power to achieve -160dBc/Hz.  This is documented in the LTC6957 datasheet.   There is an app circuit on the last page of the LTC6957 datasheet that shows an example of how to boost your input signal at 10M.  For more details see Design Note 514.  Something like this may help the HMC7043.  

With the LTC69657-1, I saw -158'ish at 10k today with 0dBm input without the application circuit, but to do this I had to remove the 50 ohm terminations. My guess this is removing some of the resistor noise and/or  increasing the voltage slew rate.  FILTA=FILTB=L.   

IN+: 0dBm --> cap --> LTC6957 IN+

IN- -->cap to GND 

I've also started looking at the LTC6955 today.  The buffer version of the LTC6953.  Similar conclusion, the 10k number will be the challenge at the low of amplitude.  A larger input amplitude would help the LTC6955/53.

For all measurements discussed above, I used this circuit on the output https://ez.analog.com/clock_and_timing/f/q-a/101357/ltc695x-low-frequency-phase-noise-measurement-issues/301260#301260 to avoid instrument induced errors.

Hi Chris

The LT1963 is used as power supply for HMC7043 and LTC6957-3. In next revision we will replace LTC6957-3 with LVPECL version.

Actually I have two LTC6957 in our system and measurements. The first one is in the reference input (10MHz) for HMC7044. The second one is separated on a board for measurements with phase noise.

Anyway LTC6957 or mentioned discriminator circuit fixes problem with measuring phase noise offsets which don't care us (above 10kHz). We focus at 10Hz to 1kHz.

I have also checked the LTC6955, but I can't compare phase noise performance on 10Hz to 1kHz offsets with LTC6953 from datasheet.

Dan

Dan, 

Thanks.  The LTC6955 is a stripped down version of the LTC6953.  We basically just disabled some circuits on the LTC6953 to make the LTC6955..  The LTC6955 will be the same or better than the LTC6953 in all cases.

I've been meaning to look at the LT3045 vs the LT1963 at low offsets for other reasons with the LT695x parts.  I think your comment here will move this test on the priority list.

Hi Chris,

I have no idea how LT3045 as replacement for LT1963 will affect performance phase noise at low offsets but the power supply of these parts will be surely revised in next revision of our hardware. Thank you for suggestions.

The used OCXO or another clock sources with low amplitude or sinus outputs are always fed through LTC6957 to HMC7043 input or directly to used ADc. I don't know about any better option for this task.

Anyway I'm gonna order eval boards with LTC6953(5) and LT3045 (if it handle LTC6953 with one output). This chip looks more promising for our application than HMC7043 (https://ez.analog.com/clock_and_timing/f/q-a/101399/hmc7044-hmc7043-vs-ltc6952-ltc6953). I don't know reason behind HMC7043's specification for 200MHz.

LTC6955 can be considered only with perceptible performance at low offsets, otherwise combination LTC6955 and LTC6953 in design is unnecessary complicated for us.

Is possible that OCXO phase noise requirements will be changed to better values. We just need to figure out the limitations of available solutions which are JESD204B compliant.

Thanks and regards,

Dan

If the LTC6953 is powered up with all outputs on it will exceed the LT3045 current.  There are few work arounds, I listed a few options in no particular order.

1) Set the LTC6953 !SD pin low on power up. Program the LTC6953 SPI to your desired configuration (one output mentioned above).  Then set !SD pin high, at this point the LTC6953 will be ~130mA

2) Load share mutliple LT3045s (see eval board DC2637A - 4 LTC3045s = 2A).  In theory this should reduce the LDO noise, which is a nice feature.  noise reduced by dividing the LDO noise by sqrt (# of load shared 3045s)

3) you can also consider ADM7150 or ADP7156 LDOs, which have 800mA & 1.2A, current respectively.