I would like to PLL a low phase-noise 10MHz OCXO to 1PPS as well as an external 10MHz reference. This looks to be a subset of the functionality offered by the AD9544/5 clock chips. However, a key requirement is the 10MHz OCXO is PLL'd as I can't accept any phase noise degradation resulting from using the internal on-chip VCO. This raises the concern that a system clock I have availble in the application of 50 or 100MHz, (which are both multiplied from the 10MHz OCXO), is the clock that is being controlled. It could be this results in a problem of positive feedback where the TDCs that rely on the system clock to phase compare the reference to the OCXO are having the system clock tuned by the TDCs output. However, both TDCs are presumably on the same clock, so maybe I am overthinking this possible problem. I am reluctant to provide a separate free-running clock as spurious, even at low levels, are a concern for my application.
A look at the External Zero Delay feature with the OCXO fed back to a REF input using the AD954x internal PLL indicates this only results in tuning the on-chip VCO frequency available at OUTXY, which I can't use. Is it possible to extract the output of the on-chip DPLL for processing and application to a DAC to tune the OCXO? I need to close the loop by tuning the OCXO with a loop BW of around 10 to 100 milliHertz.
Perhaps a more realistic approach is to use the timing skew measurement processor, as the time (phase) error is accessible digitally for processing in an external FPGA DPLL applied to the OCXO through a DAC. It seems this approach will require external frequency prescaling for the case of a 1Hz reference being compared against the 10MHz OCXO. But the concern about PLL'ing the system clock remains with this approach.
Can I use the timing skew measurement digital-output phase detector to tune the system clock a fraction of a Hz to phase lock to external references? The OCXO tuning voltage will first be calibrated, so the start up frequency error will be minimal.