AD9544 (or AD9545) 10MHz OCXO 1PPS and 10MHz PLL application

I would like to PLL a low phase-noise 10MHz OCXO to 1PPS as well as an external 10MHz reference.  This looks to be a subset of the functionality offered by the AD9544/5 clock chips.  However, a key requirement is the 10MHz OCXO is PLL'd as I can't accept any phase noise degradation resulting from using the internal on-chip VCO.  This raises the concern that a system clock I have availble in the application of 50 or 100MHz, (which are both multiplied from the 10MHz OCXO), is the clock that is being controlled.  It could be this results in a problem of positive feedback where the TDCs that rely on the system clock to phase compare the reference to the OCXO are having the system clock tuned by the TDCs output.  However, both TDCs are presumably on the same clock, so maybe I am overthinking this possible problem.  I am reluctant to provide a separate free-running clock as spurious, even at low levels, are a concern for my application.

A look at the External Zero Delay feature with the OCXO fed back to a REF input using the AD954x internal PLL indicates this only results in tuning the on-chip VCO frequency available at OUTXY, which I can't use.  Is it possible to extract the output of the on-chip DPLL for processing and application to a DAC to tune the OCXO?  I need to close the loop by tuning the OCXO with a loop BW of around 10 to 100 milliHertz.

Perhaps a more realistic approach is to use the timing skew measurement processor, as the time (phase) error is accessible digitally for processing in an external FPGA DPLL applied to the OCXO through a DAC.  It seems this approach will require external frequency prescaling for the case of a 1Hz reference being compared against the 10MHz OCXO.  But the concern about PLL'ing the system clock remains with this approach.

Can I use the timing skew measurement digital-output phase detector to tune the system clock a fraction of a Hz to phase lock to external references?  The OCXO tuning voltage will first be calibrated, so the start up frequency error will be minimal.

Parents
  • +1
    •  Analog Employees 
    on Oct 17, 2019 12:57 PM

    Hi,

    In short, all outputs that come from the AD9545/4 devices originate from one of the internal VCOs (Either the System clock PLL VCO or the APLL VCOs) which are phase locked to an external reference as these devices are jitter cleaner devices. It seems that you believe this is not an option for your application. Additionally, these products have no way to directly tune an external oscillator so you are correct in that you will need to manage the tuning of the OCXO outside of the scope of the AD9545 and you will likely need an additional buffer to create multiple copies of the OCXO output, as the distribution from the AD9545/4 is driven only by the output of one of the aforementioned internal VCO PLLs.

    First, I want to say that the AD9545/4 both have internal reference dividers which you can use to divide the 10 MHz OCXO input down to 1 Hz for direct comparison to the 1 Hz reference input. There is no need for external frequency pre-scaling.

    WRT reading the output of the DPLL loop filter:
    This can be done via the tuning word history (TWH). You could configure the device for external zero-delay operation with the input source as your 1 Hz input and the feedback source as your 10 MHz OCXO divided down to 1 Hz and then read the TWH output every second, compute the difference between the TWH and the FTW (DPLL free-running tuning word) to get the error signal, scale the error signal to account for the gain of your tuning element, and use the resulting value to tune the OCXO.

    Just be sure to disable the DPLL control bits which gate the TWH output until lock (R0x100E[5:3] for DPLL0 and R0x140E[5:3] for DPLL1).

    WRT using the skew measurement block:
    This could be used as a phase detector, but it has a minimum averaging value of 2 which would complicate things. I do not recommend this.

    Instead, I recommend using the User Time Stampers (UTS) of the AD9545 which effectively outputs the results of the TDCs to the register map. Use the same clock input configuration from above and enable one UTS to capture the 1 Hz reference timestamps and the other to capture the 10 MHz/10,000,000 feedback signal timestamps. Then you can then implement the phase detector functionality (i.e.minimal required processing is to compute the offset between the reference and feedback timestamps) and loop filter externally to drive the tuning of the OCXO.

    The  fractional frequency offset of the system clock LO will have only a minor effect on the gain of the external phase detector and can safely be ignored.

Reply
  • +1
    •  Analog Employees 
    on Oct 17, 2019 12:57 PM

    Hi,

    In short, all outputs that come from the AD9545/4 devices originate from one of the internal VCOs (Either the System clock PLL VCO or the APLL VCOs) which are phase locked to an external reference as these devices are jitter cleaner devices. It seems that you believe this is not an option for your application. Additionally, these products have no way to directly tune an external oscillator so you are correct in that you will need to manage the tuning of the OCXO outside of the scope of the AD9545 and you will likely need an additional buffer to create multiple copies of the OCXO output, as the distribution from the AD9545/4 is driven only by the output of one of the aforementioned internal VCO PLLs.

    First, I want to say that the AD9545/4 both have internal reference dividers which you can use to divide the 10 MHz OCXO input down to 1 Hz for direct comparison to the 1 Hz reference input. There is no need for external frequency pre-scaling.

    WRT reading the output of the DPLL loop filter:
    This can be done via the tuning word history (TWH). You could configure the device for external zero-delay operation with the input source as your 1 Hz input and the feedback source as your 10 MHz OCXO divided down to 1 Hz and then read the TWH output every second, compute the difference between the TWH and the FTW (DPLL free-running tuning word) to get the error signal, scale the error signal to account for the gain of your tuning element, and use the resulting value to tune the OCXO.

    Just be sure to disable the DPLL control bits which gate the TWH output until lock (R0x100E[5:3] for DPLL0 and R0x140E[5:3] for DPLL1).

    WRT using the skew measurement block:
    This could be used as a phase detector, but it has a minimum averaging value of 2 which would complicate things. I do not recommend this.

    Instead, I recommend using the User Time Stampers (UTS) of the AD9545 which effectively outputs the results of the TDCs to the register map. Use the same clock input configuration from above and enable one UTS to capture the 1 Hz reference timestamps and the other to capture the 10 MHz/10,000,000 feedback signal timestamps. Then you can then implement the phase detector functionality (i.e.minimal required processing is to compute the offset between the reference and feedback timestamps) and loop filter externally to drive the tuning of the OCXO.

    The  fractional frequency offset of the system clock LO will have only a minor effect on the gain of the external phase detector and can safely be ignored.

Children
  • Thanks for the detailed response.

    In short, all outputs that come from the AD9545/4 devices originate from one of the internal VCOs (Either the System clock PLL VCO or the APLL VCOs) which are phase locked to an external reference as these devices are jitter cleaner devices. It seems that you believe this is not an option for your application.

    The OCXO has phase noise of -120dBc/Hz at 1Hz offset and 1 second ADEV of 2E-13.  My application is an all-digital narrow BW PLL, not clock distribution.  I guess it is still a jitter cleaner, but to a noise level lower than that available from the on-chip PLL/VCO.

    WRT reading the output of the DPLL loop filter:
    This can be done via the tuning word history (TWH). You could configure the device for external zero-delay operation with the input source as your 1 Hz input and the feedback source as your 10 MHz OCXO divided down to 1 Hz and then read the TWH output every second, compute the difference between the TWH and the FTW (DPLL free-running tuning word) to get the error signal, scale the error signal to account for the gain of your tuning element, and use the resulting value to tune the OCXO.

    Just be sure to disable the DPLL control bits which gate the TWH output until lock (R0x100E[5:3] for DPLL0 and R0x140E[5:3] for DPLL1).

    It might make sense to utilitze the on-chip DPLL, if possible.The minimum loop bandwidth available for the DPLL is specified as 0.1Hz, which would include the on-chip VCO tuning sensitivity.  I didn't find this parameter specified in the datasheet, probably because a standard implementation of the part doesn't require loop calculation with an external oscillator.  Are details of the DPLL/VCO available to facilitate calculation of scaling and loop dynamics?  Or perhaps this is an argument in favor of using an external all-digital PLL.

    The OCXO total tuning range is about 6 to 10E-7.

    WRT using the skew measurement block:
    This could be used as a phase detector, but it has a minimum averaging value of 2 which would complicate things. I do not recommend this.

    Instead, I recommend using the User Time Stampers (UTS) of the AD9545 which effectively outputs the results of the TDCs to the register map. Use the same clock input configuration from above and enable one UTS to capture the 1 Hz reference timestamps and the other to capture the 10 MHz/10,000,000 feedback signal timestamps. Then you can then implement the phase detector functionality (i.e.minimal required processing is to compute the offset between the reference and feedback timestamps) and loop filter externally to drive the tuning of the OCXO.

    So the AD9544 without Auxilliary NCOs, TDCs and no mention of skew measurement or time stampers is ruled out for the approach using User Time Stampers as a phase detector in favor of the AD9545.