Hello!
Thank you for your time and help!
I try to use a clock generator chip AD9518-4 to get two 256MHz clocks form 10 MHz reference, the R divider is 5 so the frequency to PFD
is 2MHz . I set N divider =768 with B =48 and P=32. But I can't get the clock locked. DLD is low and reg at 0x01f LSB is 0. The CP pin is 3.3V which means charge pump try to raise VCO frequency and didn't get it . I set the Status Pin to show the N divider output and found the its frequency is only 900kHz and unstable,which should be 2MHz . loop filter is 54.8kHz and phase margin 40 deg designed by ADIsimCLK. Refmon pin showed Selected reference to PL is good and Status of selected reference is High. Is this mean REFin is good for the PLL and needed not be considered ??
please tell me how to solve the problem and complete the design
deisgn information
(1)loop filter design
(2) eval software design
(3) reg settings and sequences
ret=ad9518_spi_write(dev, 0x0000, 0xbd); //set SPI port miso
ret=ad9518_spi_write(dev, 0x0232, 0x01);
ret=ad9518_spi_write(dev, 0x0000, 0x99);
ret=ad9518_spi_write(dev, 0x0232, 0x01);
ret=ad9518_spi_write(dev,0x0010,0xCC); //8bit low for up frequency
ret=ad9518_spi_write(dev,0x0011,0x05);
ret=ad9518_spi_write(dev,0x0012,0x00);
ret=ad9518_spi_write(dev,0x0013,0x00);
ret=ad9518_spi_write(dev,0x0014,0x18);
ret=ad9518_spi_write(dev,0x0015,0x00);
ret=ad9518_spi_write(dev,0x0016,0x06);
ret=ad9518_spi_write(dev,0x0017,0x10); //status is P divoder output
//ret=ad9518_spi_write(dev,0x0018,0x60);
ret=ad9518_spi_write(dev,0x0019,0x00);
ret=ad9518_spi_write(dev,0x001A,0x00); //DLD
//ret=ad9518_spi_write(dev,0x001B,0x60); //refmon 0x62 ref2 0x61 ref1
ret=ad9518_spi_write(dev,0x001B,0xE1); //1 for Ref1，2 for ref2 8bit=VCO monitored
ret=ad9518_spi_write(dev,0x001C,0x06); //0x46 ref2 0x06 ref1
ret=ad9518_spi_write(dev,0x001D,0x00);
ret=ad9518_spi_write(dev,0x001E,0x00);
ret=ad9518_spi_write(dev,0x00F0,0x0A);
ret=ad9518_spi_write(dev,0x00F1,0x0A);
ret=ad9518_spi_write(dev,0x00F2,0x08);
ret=ad9518_spi_write(dev,0x00F3,0x08);
ret=ad9518_spi_write(dev,0x00F4,0x0A);
ret=ad9518_spi_write(dev,0x00F5,0x0A);
ret=ad9518_spi_write(dev,0x0190,0x00);
ret=ad9518_spi_write(dev,0x0191,0x80);
ret=ad9518_spi_write(dev,0x0192,0x00);
ret=ad9518_spi_write(dev,0x0193,0xBB);
ret=ad9518_spi_write(dev,0x0194,0x80);
ret=ad9518_spi_write(dev,0x0195,0x00);
ret=ad9518_spi_write(dev,0x0196,0x00);
ret=ad9518_spi_write(dev,0x0197,0x80);
ret=ad9518_spi_write(dev,0x0198,0x00);
ret=ad9518_spi_write(dev,0x01E0,0x04);
ret=ad9518_spi_write(dev,0x01E1,0x02);
ret=ad9518_spi_write(dev,0x0230,0x00);//04 no sync
ret=ad9518_spi_write(dev,0x0232,0x01);
//VCO calibration
ret=ad9518_spi_write(dev,0x0018,0x60); //VCO calibration low
ret=ad9518_spi_write(dev,0x0232,0x01);
ret=ad9518_spi_write(dev,0x0018,0x61); //VCO calibration begin
ret=ad9518_spi_write(dev, 0x0232, 0x01);
mdelay(50);
ret=ad9518_spi_write(dev,0x001D,0x0D);
ret=ad9518_spi_write(dev, 0x0232, 0x01);//enable hold over
ret=ad9518_spi_write(dev,0x0017,0x04);//status is N divoder output
ret=ad9518_spi_write(dev, 0x0232, 0x01);
(4)schematic
Thank you for your time and help, I appreciate a lot!
best wishes !
Yu Ping
