How to config the AD9517-3 registers(fine delay ) to produced 180-degrees LVDS Outputs?

hello guys.

I design the processing board that contains the AD9517-3, tow AD9643, and Kintex-7 FPGA.

The AD9517-3 LVDS outputs directly connected to AD9643 input_clk and FPGA HP banks; tow AD9643 ADCs works with 250 Mhz that AD9517-3 drives them. The ADCs work correctly but I want to set one ADC works with 0-degree and another by 180-degrees input_clk.

According to the AD9517-3 datasheet, fine delay block must be added to the LVDS output that output shifted to 180-degree,

please help me to config the AD9517-3 registers to LVDS fine Delay that 180-degrees produced.

best regards,

  • 0
    •  Analog Employees 
    on Sep 12, 2019 12:59 PM over 1 year ago


    the easiest way to obtain a 180 degree offset into a differential signal is to connect it vice versa to the receiver. 

    If you want to introduce the phase offset, the data sheet provides the procedure to introduce a phase offset into the Dividers 2 and 3  at page 46. You need to know the frequency of the input clock to the dividers (which you did not provide in this email). Then, please note that the output can be delayed only by up to 31 input clock cycles, so depending on what divider ratio you chose, you may not be able to delay  by 180 deg.