I design the processing board that contains the AD9517-3, tow AD9643, and Kintex-7 FPGA.
The AD9517-3 LVDS outputs directly connected to AD9643 input_clk and FPGA HP banks; tow AD9643 ADCs works with 250 Mhz that AD9517-3 drives them. The ADCs work correctly but I want to set one ADC works with 0-degree and another by 180-degrees input_clk.
According to the AD9517-3 datasheet, fine delay block must be added to the LVDS output that output shifted to 180-degree,
please help me to config the AD9517-3 registers to LVDS fine Delay that 180-degrees produced.