Hello, ADI expert:
My current demand is: there are multiple boards, each board outputs (generates) 4 channels of 150M IF, each channel needs to be synchronized (output phase difference can be coherent), the spur is better than 60dBc; the data source is FPGA, IQ data The data clock is 100M, the baseband bandwidth is lower than 30M, and the current DAC sampling clock is 800MHz externally provided.
Question 1: Through the selection of ADI's official website, it is found that the AD9957 interface design is relatively simple. If you want to use it, I don't know if this DDS can meet my needs. Whether the phase difference between the channels can be made constant after the AD9957 multi-chip synchronization. Question 2: I want to achieve IF output synchronization between the various boards, but the sync signal comes from the outside, I don't know what specific parameters are required for the sync signal. For example, what are the specific requirements for the pulse width, period, and jitter of the sync signal? I now pass the external sync pulse signal through a low-jitter splitter and then distribute it to the SYNC_IN pin of the AD9957 in each board through multiple cables. If the cable is not equal in length, it will affect the synchronization. Is there a recommended connection method to resolve synchronization issues between multiple boards? Question 3: (One IF output requires one AD9957, and the power consumption is also high). Does ADI have a better solution, for example, a single chip can directly realize two IF outputs. If there is a high-speed DAC with lower power consumption to meet my needs, I hope to provide a reference.
Thank you! ! !
Moved to Clock and Timing forum.