We have a custom design. We are supplying a 3.3V 50MHZ OCXO CMOS clock to the XOA input. We have followed the design recommendations in Figure 30, page 45 of the datasheet. This divides the CMOS input by a 330/150 ohm divider and ac couples using a 0.1uF capacitor. XOB has a 0.1uF capacitor to ground. Bit 3 of 0x0201 is cleared, crystal amplifier disabled. Bit 0 of 0x0201 is cleared, clock doubler is disabled. Bit 0 of 0x3001 of set, SYSCLK is locked. Bit 1 of 0x3001 is cleared, SYSCLK is not stable.
0x0200,0x30, // 48 == 0x30 divide by 48, 2.4Ghz PLL output
0x0201,0x00, // no multiply, no crystal amplifier
0x0202,0x00, // 50000000000 == 0x0BA43B7400
Status from 0x3001 == 0x01
What can we do to get SYSCLK stable?
Please provide the values programmed into registers 0x0207 to 0x0209. If these are 0, then this is a special mode of the 9545 that indicates an unstable status of the SysClk REGARDLESS of its actual status. See page 49 of Rev B datasheet.
Yes, they were 0, Thank you for the assistance!
I have now set them to the following:
0x0207,0x32, //50 milliseconds 0x0208,0x00, 0x0209,0x00,
I appreciate your help. This has been resolved.