AD9545 SYSCLOCK will lock but never become stable

We have a custom design. We are supplying a 3.3V 50MHZ OCXO CMOS clock to the XOA input. We have followed the design recommendations in Figure 30, page 45 of the datasheet. This divides the CMOS input by a 330/150 ohm divider and ac couples using a 0.1uF capacitor. XOB has a 0.1uF capacitor to ground. Bit 3 of 0x0201 is cleared, crystal amplifier disabled. Bit 0 of 0x0201 is cleared, clock doubler is disabled. Bit 0 of 0x3001 of set, SYSCLK is locked. Bit 1 of 0x3001 is cleared, SYSCLK is not stable.

 

    0x0200,0x30, // 48 == 0x30 divide by 48, 2.4Ghz PLL output

    0x0201,0x00, // no multiply, no crystal amplifier

    0x0202,0x00, // 50000000000 == 0x0BA43B7400

    0x0203,0x74,

    0x0204,0x3B,

    0x0205,0xA4,

    0x0206,0x0B,

 

Status from 0x3001 == 0x01

What can we do to get SYSCLK stable?