HMC7044 cycle slip not working on all outputs, with low value of N2 divider

Hi all,

We use the HMC7044, and we want to use (multi)cycle slipping for clock phase adjustment. 

To test the cycle slipping, I program a low output frequency (i.e. 1MHz), and enable cycle slipping. On some of the channels this works, on some it doesn't. I have tried multi-cycle slipping, and single-cycle slipping, but still the same.

I have found the issue on our project board, but verified this on the HMC7044 eval board (changed VCXO from 122MHz to 100MHz).

Some settings, in this case cycle slipping does not work for all channels:

  • PLL1 VCXO = 100MHz
  • Freq. doubler = ON
  • R2 divider = 1
  • --> PFD2 input frequency = 200MHz
  • N2 divider = 12
  • --> VCO frequency = 2400MHz.

With these settings, cycle slipping does work properly:

  • PLL1 VCXO = 100MHz
  • Freq. doubler = ON
  • R2 divider = 2
  • --> PFD2 input frequency = 100MHz
  • N2 divider = 24
  • --> VCO frequency = 2400MHz.

With these settings, cycle slipping does also work properly:

  • PLL1 VCXO = 100MHz
  • Freq. doubler = OFF
  • R2 divider = 1
  • --> PFD2 input frequency = 100MHz
  • N2 divider = 24
  • --> VCO frequency = 2400MHz.

Does anyone else see this issue?

Is there a setting I am missing?

It seems like increasing N2 from 12 to 24 gets it working. Is there a limitation on N2 divider for cycle slip to work? I chose highest PFD2 frequency for best jitter performance.

If I limit N2 values to a minimum value, does this solve the problem for all other frequencies? What would be the minimum value for N2?

Any feedback is appreciated.