I have a problem in that my SYNC pin does nothing - unresponsive. I have read the relevant posts (and others)
I have a state machine running off of the OSCOUT0 pins ( at 125 MHz ) that fires the SYNC pin ( tried one and 8 VCXO cycle(s) ). I have the registers
0x0005 bits [7:6] set to '01' (SYNC. A rising edge is carried through PLL2. Useful for multichip synchronization.)
0x005B set to 0x02 ( SYNC through PLL2 Allow a reseed event to be through PLL2 )
as well as the appropriate bits to enable the channels in question. The channels respond to a register 'Restart Dividers/FSMs' bit 1 of reg 0x0001. How can I get the Sync pin to respond and restart the dividers?
Do you have the evaluation board? Can you post your settings from the evaluation board software?
What would you expect to see when you toggle the SYNC pin?