I'm using ADN4662 for LVDS to CMOS conversion.
I have observed a 200MHz oscillation at it's output with no Input AC waveform.
I have included the 100E termination across 1 & 2 and 1.6V bias at pin 1.
In one PCB the oscillation has 3Vpp and second PCB has 2.2Vpp.
ADN4662 has failsafe output state (output stays stable logic high) for only one condition, open circuit. With 100 Ohm termination across the inputs, the input is not open circuit, but looks similar to a short circuit with ~0V differential. The receiver thresholds are +100 mV for logic high or -100 mV for logic low, so in between, the output is indeterminate, as you've observed (the exact signal observed will vary and probably depends on the power supplies and noise coupling).
The options are to ignore the receiver output when the input is not driven, or if the termination resistor is permanently at the receiver, the inputs can be biased to ensure a minimum of 100 mV, by placing a pull-up on Rin+ and a pull-down resistor on Rin-.