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AD9544/PCBZ Help Getting Outputs Working


    Good Afternoon!

    I am having trouble getting a signal out of the AD9544/PCBZ board.  I successfully updated the EEPROM so that the ACE software recognizes the unit as a AD9544 instead of a AD9545 and have been able to successfully lock everything; see image:

    But when I probe the outputs I get nothing, and I am not sure why.  From the user guide they are supposed to be single-end AC coupled correct? '10 ac-coupled single-ended (differential signal recombined via a balun) output SMA connectors, with user-configurable output termination for HCSL, CML, or LVDS-compatible (default)' In ACE I configured OUT0A to be HCSL, 15 mA, SE, however I get noting out on the scope. 

    Also, some other things to note... In the DPLL0, APLL0, and System Clock PLL, the DPD, PFD, and PFD all have 'Output Signal = 0 Hz', respectively.  Not sure if that is a clue. 

    It is likely there is some setting that I am missing and hopefully someone here can help point it out to me.  I appreciate the support.

    Best Regards,


    • I found the schematic online and saw that the baluns are not installed.  So now I turned off all outputs except for OUT0, set the output to HCSL, 7.5mA, and connected the P300 jumper to the vout_common.  I had an AD8130 on an evaluation board and connected it to the OUT0A/AA with 100 Ohm termination across the input. This configuration matches (or at least I pretty sure matches) what is described in Figure 31 on page 29 in the AD9544 datasheet... still no output... I'll try popping the P300 back to the 1.8V pull-up and see if that does it, but I'm doubtful. 

      I'm thinking there is something wrong in the configuration that I can't seem to figure out... again, any help would be great.

      Best Regards,


    • HI Matt,

      first, please use the AD9545 data sheet and related documentation as a proxy for the AD9544. We will update the AD9544 data sheet with the AD9545 info in the near future. The AD9544 is the AD9545 minus the auxiliary TDCs, auxiliary NCOs and embedded clock modulation/demodulation.

      Comments on the evaluation board:

      -yes, the baluns on REFA and REFB inputs are not populated.

      -The HCSL setting (jumpers P300, 301, 302, 303  and 304 between pins 2 and 3) does not work by default. You need to connect a wire between TP307 to ground to make it work. Basically, the VOUT_COMMON was left floating. 

      -The CML setting (jumpers P300, 301, 302, 303  and 304 between pins 2 and 1) works.

      Comments on the evaluation software:

      - let say you use the configuration wizard. You set it as you need and then click Apply. After this, you need to click also on Cal All, Sync All, IO Update tabs to get the outputs enabled (supposing the PLLs lock and everything else works OK)

      - then you save the session.

      -the next day, when you load the session, do not use the wizard as the setup is not transferred into it. Just click Apply changes, followed by Cal All, Sync All, IO Update tabs.

      Best regards and please keep me posted.


    • Hello Petre -

      Thank you for getting back to me.  I started a new session and followed the procedure you have outlined, however, I still do not get anything out.

      Since there are no baluns on REFA, does that mean I'll need to drive it with a differential signal for it to work?  Because right now I am going into the J300 connector with 0dBm.  The REFA Valid light is on the ACE software... I have all green lights... I've configured the M pins to show lock detection for the System Clk lock, DPLL0 phase & frequency lock, and APLL0 lock and all lights are on.

      So if I want to drive into an LVDS receiver, I'll need to set the output to HCSL, set the common mode to ground, and terminate on the receiver through 100 Ohms. Is that correct?  Is there a way to test this board directly with an oscilloscope into 50 Ohms? 

      Best Regards,


    • Petre,

      I was able to get something on the output!! Woo! High-fives all around... So, what I believe turned on the outputs was under DIST0 Settings.  I guess it's defaulted to 'disabled' and after switching that to DPLD I was now able to get a signal on the output... does that sound right?

      Best Regards,


    • Hi Matt,

      I'm glad that you got the board going, but I do not know what from DIST0 Settings menu started them. The dividers must be enabled for the outputs to function. See page 65 in rev B data sheet

      This is why I told you to press Sync All button after pressing Cal All.

      On your previous question about the HCSL: yes, make that ground connection. The outputs are already terminated with  two 50 ohms and the ac coupling caps, like figure 37 in the data sheet. Yes, you need to add a 100 ohm at the receiver.

      Best regards