I have previously and successfully configured the AD9517 to generate a 200MHz output clock using an external VCO which had a range of about 1100MHz to 1300MHz. The successful design used a 10MHz reference clock input and a 10MHZ PFD with the following:
A = 0
This design multiplied the 10MHZ reference by N= (8*15 +0) =120 to set the external VCO to 1200MHz and then an output divider of 6 gave a final output of 200MHz. With the loop filter components set in ADICLKSim, the loop gave a near ideal 45 degree phase margin and the actual circuit worked well.
In an effort to try an avoid 10MHz harmonics from getting into other sensitive nodes, I switched to use a 100MHz reference to replace the 10MHz oscillator. In the first attempt, I simply changed R from 1 to 10 and maintained the PFD at 10MHZ. This configuration worked fine and the loop stayed lock.
In my second configuration I used the 100MHz reference but set the PFD frequency to 25MHz and set the following:
A = 8
In theory, the VCO should still be at 100MHz/4 * (8*5 + 8) = 25MHz *48 = 1200MHz. In simulation this configuration gave a reduced phase margin of 29 degrees but I still expected that it would work well. The Sim program does not actually state the value of A and B but it does confirm R=4 and P=8. This configuration did NOT lock and it would instead oscillate in and out of lock. I reread the data sheet but could find no reason why this configuration was invalid or should be unstable given a 29degree phase margin???
So then I tried a new configuration with the Prescaler DM set to 16/17. In this third configuration with the 100MHz reference oscillator, the configuration of the PLL was as follows
A = 0
In theory, the VCO should still be at 100MHz/4 * (16*3 + 0) = 25MHz *48 = 1200MHz. This configuration worked correctly and the loop remain locked.
Can someone tell me if the second configuration that could not remain locked violated some configuration rule??? AT 1200MHz, the prescaler should be able to operate at 8, 16 or 32 and with P=8, R=4, B=5, and ,A = 8, the loop should have locked. Any help in understanding why this is not a valid configuration would be appreciated.