AD9528 output Slew Rate Calculating

Hi there

We use AD9528 to drive downstream CLOCK buffer ADCLK948. LVDS or HSTL. However, we noticed that ADCLK948 requires its inputs SLEW RATE > 4V/ns to ensure its specified high performace. I look into AD9528 table 8 in datasheet, seems that : 

For LVDS outputs, min. slew rate = 0.345V*60% / 216ps = 0.958V/ns. Far below the 4V/ns, which means ADCLK948's performace will be affected.

For HTSL outputs, min. slew rate = 0.9V*60% / 160ps = 3.375V/ns. neraly satisfy 4V/ns. but still not enough.

Furthermore, For LVDS the min. rise/fall time and typ.VOD is missing, For HSTL the  min. rise/fall time is missing, so I cannot calculate the max slew rate.

Is my calculation wrong? Please help give some insight. Thanks!

Parents Reply Children
No Data