We use AD9528 to drive downstream CLOCK buffer ADCLK948. LVDS or HSTL. However, we noticed that ADCLK948 requires its inputs SLEW RATE > 4V/ns to ensure its specified high performace. I look into AD9528 table 8 in datasheet, seems that :
For LVDS outputs, min. slew rate = 0.345V*60% / 216ps = 0.958V/ns. Far below the 4V/ns, which means ADCLK948's performace will be affected.
For HTSL outputs, min. slew rate = 0.9V*60% / 160ps = 3.375V/ns. neraly satisfy 4V/ns. but still not enough.
Furthermore, For LVDS the min. rise/fall time and typ.VOD is missing, For HSTL the min. rise/fall time is missing, so I cannot calculate the max slew rate.
Is my calculation wrong? Please help give some insight. Thanks!
Apologies for the late response. Here is my insight regarding your question. The values you obtained from your calculation is correct. These slew rates would be the minimum slew rate that the AD9528 would have in the worst case scenario. For the missing data you need to calculate the maximum slew rate, you could use the typical rise/fall time instead. The maximum slew rate for LVDS would be 4.68V/ns and for HSTL would be 11V/ns. Using the typical values, using the average of the minimum and maximum VOD as the typical value, the typical slew rate for LVDS would be 4.41V/ns and for HSTL would be 10V/ns which are above the 4V/ns specification. Thus, the typical performance of the AD9528 with any output type would ensure the ADCLK948 to be on its highest performance.
hi Mark, are you still there?
Sorry for overlooking this. Yes you are partially correct. The differential voltage for HSTL should be 2x(900mV to 1100mV) because they represent VOH-VOL on each output. So the typical slew rate is (2*1000mV*0.6)/60ps giving us a value of 20V/ns. Then the lowest slew rate is (2*900mV*0.6)/160ps which is 6.75V/ns. As for the max slew rate, I think we should not care about this since it would be greater than the 4V/ns recommended value. As for LVDS, its driver is a current source with 3.5mA and 100 ohm load. Thus, the differential voltage across the resistors is typically 350mV. The typical slew rate is (350mV*0.6)/50ps that is equal to 4.2V/ns. Then the lowest slew rate is (345mV*0.6)/216ps that would be 0.96V/ns which would be the worst case. So using HSTL produces a better slew rate than LVDS. With HSTL, the 1.8Vp-p min and 2.2Vp-p max differential voltage is within the ADCLK948 requirements of 0.4Vp-p to 3.4Vp-p. So AC decoupling the HSTL output of the AD9528 and plugging it to the ADCLK948 would not cause any performance problem.