AD9515 Slew Rate minimum Requirement

i'm going to use AD9515 chip in my design for converting 100MHz signal to 10MHz signal
Slew Rate calculation: for 100MHz 1 cycle time will be 10ns. So, if i divide it by 4 maximum peak voltage point can be obtained at 2.5ns.
 
I'm providing the input of 0.35V.
 
So, my slew rate will be =0.35V/2.5ns  => 0.14V/ns. (it is not meeting the spec. of minimum 1V/ns)
 
I want to know
 
1) Whether I can use that chip for 100MHz with 0.35V Peak power ?
 
2) whether the above slew rate calculations are correct ?
3)provide the input slew rate vs output  jitter plot ?
  • 0
    •  Analog Employees 
    on Feb 11, 2019 6:20 PM

    Hi,

    could you please tell me if the 100 MHz input clock is a square wave or a sinusoidal wave?

    Because in the case of the square wave, the slew rate is the ramp of the square.

    In case of a sinusoidal wave, the slew rate is Vpeak*(2*PI*f)/1E9 (V/ns). For a sinusoid with a peak value of 0.35Vp, the slew rate is then 0.35*(2*PI*100E6)/1E9=0.22 V/ns.

    Yes, the data sheet says that if the slew rate is lower than 1V/ns, the jitter performance is degraded (page 18). You would need a signal with 1V/ns*1E9/(2*PI*100E6)=1.592Vp amplitude to meet that requirement.

    The data sheet does not have a diagram quantifying the jitter degradation, so it is very hard to quantify it. You may take an evaluation board, try it and see if the performance is acceptable to you.

    Or you may want to take a look at the AD9508: it has dividers to bring the 100 MHz to 10 MHz and it has the figure 25, page 17 in the data sheet that shows the degradation in jitter function of the slew rate:

    Best regards

    Petre

  • Hi,

    Thank you for the reply,

    i'm using VCXO 100MHz Sine wave Reference source Part No. CVSS-945X-100.000.