Using PLL2 directly in HMC7044


I am trying to understand the possible ways in which I can use HMC7044 to generate clocks to drive fast wideband RF ADC (like the AD9208).  But I have 2 questions:

(1) How do I simply make HMC7044 run from a 10MHz reference input (from another lab source) if I didn't care about jitter/synch performance: do I have to input that to PLL1 as one of its inputs (say CLKIN0) or can I just bypass PLL1 and input that source directly to the OSCIN input to work with PLL2 (without PLL1)?  And using the Evaluation Kit (EVAL-HMC7044), which has an on-board VCXO connected to PLL1 already, can I disable this somehow so that I can use the OSCIN input to inject the external 10MHz reference directly to drive PLL2?

(2) Another more general question is this: if I didn't care about locking to a external reference signal or synch with any source at all, and only wanted to use HMC7044 as a standalone clock generator, how can I use PLL2 only without caring about the inputs of PLL1 (i.e. no connections to inputs)? Is that possible? If yes, can you please explain how?

Many thanks

  • 0
    •  Analog Employees 
    on Jan 30, 2019 3:47 PM over 1 year ago

    1) It is possible to disable PLL1 and run a reference directly to PLL2.  On the back of the board remove jumpers from the VCXO to the OSCIN traces.  Also install the OSCIN SMAs, to connect your reference to the HMC7044.  It would be best to power down the VCXO also, so the VCXO frequency does not create unwanted spurs elsewhere on the board.   

    The reference outputs on the back of lab instruments  usually have pretty poor phase noise.  These reference typically degrade the performance of our high performance parts.  Below is an example of another PLL/VCO that doesn't use a clean up loop with different reference sources.  Notice how much the 10MHz reference from the test instruments(spectrum analyzer) degrades performance.   Just a word of caution if you are interested in getting the best performance out of the a high performance PLL/VCO.  The clean up loop will help.

    2)  you can connect the reference input to OSCIN and look PLL2 to the reference.  The HMC7044 software allows you to disable PLL1.

  • Hi Chris,

    Many thanks for your kind advice. 

    I hope you will bear with me, as I try to understand and learn how to operate this system.

    (1)  I read the datasheets, but I am finding it really difficult to get PLL1+PLL2 to lock to an reference input on CLKin0. Is there any tutorials or videos or case studies (other than the datasheets) that show a practical way to use the EVAL board for HMC7044 and its software?

    For example, the EVAL board has 122.88MHz VCXO onboard already. I tried to give it a reference input (CLKin0) of 4*122.88=491.52MHz, and set Prescalar1 to 4, with Prescalar for VCXO to 1 (to get their least common multiplier, which is 122.88MHz), but nothing is happening. I am not sure why.  My reference input level is sinusoidal -0.6V to +0.6V (so around 5.5dBm) .

    I tried to find out where is the issue, so i disabled PLL2 and I checked if PLL1 is working by looking at the signal OSCout1, but I could only find (on the spectrum analyzer) lines at 10MHz and 122.88MHz and the harmonics of 122.88MHz (even harmonics always around 20 dB lower than odd harmonics)... I am not sure why it is not giving any synthesized frequency: Fref*(N1/R1), even when I play with the N1 and R1 values.

    For example, can you give me an example of setup values that should work, to check it out?

    The only thing that is working OK so far is the output stages when I give them direct signal reference on CLKin1/Fin (bypassing both PLLs). But that is not very helpful.

    Any suggestions to help running it would be great. Also, if there is anyone from Analog Devices who you know we can contact it would be great.

    (2)  By the way, we noticed that the power supply total current when the board is reset is actually 800mA for 5V (not the typical 586mA stated in datasheets). Is this 800mA on power-up normal?  Note that it reduced to 300mA or so when we disable some PLLs.

    (3)  Is there an easy way to understand and learn about Synching and SYSREF and JSED204B basics quickly?  For example, I need to generate from HMC7044 signals that would drive the Evaluation boards of AD9208 and its FPGA acquisition card (ADS7). What signals do i need to get out of HMC7044 for this?

    Looking forward to your kind advice.