AD9528 jitter question

Hi, any ADI guys could help on this?  Thanks.

Chapter 9 Hardware Design Techniques F.pdfHi XY,

let me respond to your questions:

If we use Buffer Mode, Output Additive Jitter is about 140fs. so total rms jitter for AFE ADC clocks should be roots.quare(100*100+140*140+54*54) = 180.3fs rms. Is my perception correct?

Yes. It seems you are focusing on using LVDS outputs and are concerned only about the12kHz to 20 MHz frequencies. Please note that these numbers were obtained using an external 122.88 MHz source driving VCXO inputs, which may not be your case. Then, please pay attention to the slew rate of the inputs. The figure 19, page 21 in the data sheet shows the rms jitter increases very fast for slew rates below 0.25V/ns:

2. If we use PLL Mode, OUTPUT 【Absolute】 Time Jitter is about 179fs. For the "Absolut jitter", does is mean , there is no need to consider jitter of Crystal ? Not sure about this.

Yes, the absolute jitter includes all the source noises that come into the chip, not only the noise created by the chip (which is the additive noise).

3. For AFE ADC GND layout, is it necessray to seperate Analog GND and Digital GND, and connect them at one point? Or could we use one complete GND plane? 

This is what the theory says. Please take a look at the attached Hardware Design Techniques chapter (page 9.32, figure 9.22)  of the Data Conversion Handbook that you can find here:

https://www.analog.com/en/education/education-library/data-conversion-handbook.html

But the easiest approach is to copy the layout of the AD9276 from its evaluation board. I see an evaluation board manual (UG-016) that contains the schematic and the layout. Gerber files are provided on its webpage.

2. Any suggestions on CWx16 clocks jitters selection? Also, guidance on layout and routing about CW siganl is appreciated

Please note I do not know the AD9276, but I suggest following the layout of the evaluation board.

Best regards

Petre

Hi Petre,

Thanks for helpful answers. You indeed reminded, and I re-checked the Crystal 's output slew rate, it's above 0.5V/ns, so it is ok to be AD9528 input.

We have one additional question about AD9528, hope you could help to take a look.

Suppose we use ADCLK948 as downstream clock buffer after AD9528. For LVDS output of AD9528(Table.8), Diff. Output Swing (Vod) min. is 345mV, and max. rising time is 216ps, which means AD9582's LVDS output slew rate is min. (80%-20%)*345mV / 216ps = 0.96V/ns. This is far smaller than ADCLK948 requirement (>4V/ns), and its low additive jitter performance will be degraded (Fig,12 of ADCLK948 datasheet). 

Of cousre, if we only look at AD9528 LVDS output Typical rising time 50ps, slew rate will not be a problem.

Is my understanding correct? And any suggustion for this situation? Thanks, and hope you good weekends.

Hi Petre,

Quote:  It seems you are focusing on using LVDS outputs and are concerned only about the12kHz to 20 MHz frequencies. Please note that these numbers were obtained using an external 122.88 MHz source driving VCXO inputs, which may not be your case.

------XY reply:  Yes ,our external Crystal which drives AD9528's VCXO is 160MHZ or 200MHZ.  And ADC input signals' freq. range is about 1KHZ~20MHZ. 

So how may I get the jitter data at 160 or 200MHZ from existing 122.88MHZ-data?   Thanks again.

Hi Xiaoiff,

Hi,

It is not clear to me why you want to couple the AD9528 with the ADCLK948 buffer. I looked over the AD9276 data sheet and you can use an up to 80MHz clock to clock it. Cannot you obtain one directly from the AD9528?

Then, if you really need a buffer after the AD9528, you can take a look at the ADCLK846. It allows for an input clock with lower slew rates. See figure 11 from the data sheet:

Regarding your question to getting the jitter data at 160MHz or 200 MHz from existing 122.88 MHz data:

I can give you a formula to deal obtain the absolute phase noise:

 Let’s take this data from the AD9528 data sheet, page 10:

So for fout=122.88MHz, we have an absolute phase noise of -111 dBc/Hz.

For 160MHz, the absolute jitter should be around -111+ 20*log10(160/122.88)=-109 dBc/Hz

The exception is any point that scales below approximately -160 dBc/Hz (see figures 12 to 16). This is the noise floor of the output drivers which is the lower limit of the phase noise.

This rule applies because the divider of the frequency is after the PLL (that is outside of it). This makes for a simple translation of the phase noise plot. If the divider was inside the PLL, in the feedback loop, this would not have been true because this changes the BW of the PLL.

If you need the additive time jitter at the new frequency starting from known data (for example, from page 11 of the data sheet):

For 122.88MHz, we have 124fs for BW=200kHz to 5 MHz). For 160 MHz, we have 124*122.88/160=95 fs.

 Best regards

Petre

Hi Petre, 

Thanks for you patiently reply.

Our application is medical ultrasound system. End points ICs totally require more than 40 independent LVDS clocks.

Clock Tree : Crystal --> AD9528 --> Clock Buffer --> 16pcs AFEs + 16 pcs pulsers+ FPGAs + others.  This is why we have to use buffers. 

I noticed ADI have some good MT turials on basics of clocks. Could you kindly recommend some any more references or tech notes in depth, especially for clocks, phase noise, jitter and relevant topics?  

Thanks again.

mark

mark

Hi Xiaoiff,

I recommend these:

https://www.analog.com/media/en/training-seminars/tutorials/MT-008.pdf

https://www.analog.com/en/analog-dialogue/articles/pll-for-high-frequency-receivers-and-transmitters-1.html

https://www.analog.com/en/analog-dialogue/articles/pll-for-high-frequency-receivers-and-transmitters-2.html

https://www.analog.com/en/analog-dialogue/articles/pll-for-high-frequency-receivers-and-transmitters-3.html

Best regards

Petre

mark it

Hi,

I'm very sorry for the delay. I thought I have responded to this.

I recommend these:

https://www.analog.com/media/en/training-seminars/tutorials/MT-008.pdf

https://www.analog.com/en/analog-dialogue/articles/pll-for-high-frequency-receivers-and-transmitters-1.html

https://www.analog.com/en/analog-dialogue/articles/pll-for-high-frequency-receivers-and-transmitters-2.html

https://www.analog.com/en/analog-dialogue/articles/pll-for-high-frequency-receivers-and-transmitters-3.html

Regards

Petre

Hi Petre

No need to appologize. You have already answered this long time ago. I marked this post just for future use. Thanks agian. Hope you all good in 2019 work and life.