I'm planning to use AD9530 for ADC clocking.
Is it possible to generate a continuous range of frequencies using AD9530?
I need to make the clock programmable from 50MHz to 200MHz.
Any update on this?
The AD9530 can generate output clocks in the 5.725MHz to 2.7GHz range (see the specifications table in the data sheet at page 7), so it includes the range on which you focus.
One problem you will have is the "continuous range" resolution because the VCO has a very narrow range (5.11GHZ to 5.4GHz), so you have to play with the M1,M2 and channel dividers D1,D2,D3 and D4 to create frequencies in the 50MHz to 200MHz. As M1 and M2 can be 2,2.5, 3 and 3.5 and D1,D2,D3 and D4 can be anywhere between 1 and 255, you will not be able to hit every frequency imaginable in that range.
A solution to this would be to place in front of the AD9530 a DDS chip that can generate a variable reference clock and use this to obtain a finer resolution at the AD9530 clock outputs.
If you tell us the phase noise specification you need to obtain at the AD9530 outputs, we should be able to recommend a DDS product.
I expect a clock jitter better than 100ps.
We have decided to use AD9530 in our design and I procured an evaluation board for the same.
In the datasheet, the loop filter components are given for a PFD of 181.5MHz (Table 17). I'm using a VCXO of 92.16MHz.
Please suggest the loop filter configuration values for this case, since we don't have ADISIMCLK support for AD9530.
If you look at Table 9 in the data sheet:
Your VCXO is approximately 100 MHz and the output frequencies you target are from 50MHz to 200MHz, so the absolute time jitter you most probably have is between 210fs and 232fs. This number is much lower than your target of 100ps.
This data was obtained for a 8kHz loop bandwidth, so I suggest using the default filter components suggested in Table 17 that you mention.
I'm using a PFD of 92.16MHz, but the PFD for the loop filter components mentioned in Table 17 is for 181.5MHz. So I'm afraid whether the loop will go to instability.
sorry for the delay in responding. Please do not open new queries with same question. Use this trail instead.
I do not have a tool to calculate the components for the particular conditions you state. I demonstrated above that the components suggested in Table 17 in the data sheet should work very well. Did you try them on the evaluation board you have?
AD9530 did lock to the required frequency settling.
But I'm not sure whether the in-band phase noise is up to the mark. I'm feeding the reference from the signal generator for the time being.
Once I get a grip on the circuit and the IC register values, I'll replace the signal generator with a VCXO based clock synthesiser.
I'll keep you updated as I proceed with the evaluation.