25 MHz-10 MHz clock generator using clean reference. Product selection to meet strict phase noise requirements.

Hello,

 

I am seeking a clock generator (PLL or DDS) that will meet the following design specifications:

  • One fixed external 25 MHz LVCMOS input as reference
  • One fixed 10 MHz output
  • The external reference is clean so jitter cleaning/small loop bandwidth (For a PLL) is not desired. It is only required that the device does not add significantly to the phase noise from the reference
  • Phase noise contributed by the clock generator must not exceed the following targets:

 

Frequency Offset (Hz)

10 MHz Clock Output Targets

1

-70

10

-95

100

-115

1000

-140

10000

-150

100000

-160

1000000

-160

5000000

-160

                All values in dBc/Hz

I have a couple related questions:

  1. I am aware of how loop filter bandwidth influences additive phase noise for PLLs, but am still educating myself about DDS. Is DDS phase noise influenced in a similar way by the reconstruction filter?
  2. I can find candidates that meet the first two requirements, but additive (Or in DDS parlance, residual) phase noise information seems absent from most datasheets. Does analog provide simulation software (Similar to TI's Clock Architect) or additional reference information for this type of evaluation?
  3. Initial suggestions on products that might be appropriate for this application?

Preferably I would be able to screen the viable options down to a handful of candidates using reference values and/or simulation so your responses are much appreciated.

Many thanks!

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