I am seeking a clock generator (PLL or DDS) that will meet the following design specifications:
Frequency Offset (Hz)
10 MHz Clock Output Targets
All values in dBc/Hz
I have a couple related questions:
Preferably I would be able to screen the viable options down to a handful of candidates using reference values and/or simulation so your responses are much appreciated.
ADI has a tool called ADIsimPLL (https://form.analog.com/Form_Pages/RFComms/ADISimPll.aspx ), that can select and simulate most of ADI's PLL and PLL/VCO options.
Since ADI has acquired Linear Technology (LTC) recently there are a few parts not in this tool yet. There is an LTC clock part, LTC6951, that can do what you are asking for. This part uses the LTC6951Wizard (http://swdownloads.analog.com/ltc6951wizard/ltc6951wizardsetup.exe ) instead of ADIsimPLL. Under the LTC6951Wizards help menu, there is a help file with an example of how to use this tool.
You will need a pretty good reference input to generate the 1Hz to 1kHz offset numbers. Starting on page 49 of the LTC6951 datasheet is a good overview of reference input selection and concerns. The below plot uses an ideal reference for simulation, this was done to show the capability of the LTC6951. Something like Crystek's CCHD-575 series maybe a good starting point for a reference. After you have LTC6951Wizard you load the *.6951set file in the attached zip file to generate the plot shown below, this file can also be used to program the LTC6951 evaluation board if you choose to order it (https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/dc2248a-a.html). You will need the DC2026C board to allow your computer to talk to the LTC6951 evaluation hardware. (https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/dc2026c.html )
Also for generating good phase noise at low offsets you will need a very low noise supply for the CP, VCO and REF supplies. I would recommend looking at the LT3042 and LT3045 LDOs.
When investigating DDS, please make sure to read up on how the DDS's clock phase noise affects the DDS output phase noise.
Hope this helps! Good Luck!
10MHz output plot (red line)
I will look into those. Thank you Chris.