Clock synthesiser (AD9517) for ADC clocking without compromising the ADC performance.


I'm using my ADC, AD9268 for an application where the clock has to be programmable over a wide frequency range. So I've decided to use AD9517-3 for clocking the ADC. But I don't want to sacrifice the ADC SNR /ENOB performance.
I used the ADISIMCLK v1.7 software for designing/optimising the loop filter for AD9517. 
I did the simulation in two ways: (1.) using the internal VCO of AD9517-3 and (2.) using an external VCO.
In the internal VCO case the jitter performance was not upto the requirement (424fs, SNR=71.49dB), whereas with external VCO the jitter improved to 258fs, SNR=75.8dB. The phase noise of internal VCO must be bad when compared to the external VCO case.
But both the results are far off from the specification. AD9268 is havnig 78dB SNR and ENOB of 12.7bits @ 70MHz.
Is there any other clock synthesiser ICs available which can meet the requirement?


Vishnu R.

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