Clock synthesiser (AD9517) for ADC clocking without compromising the ADC performance.

Hi,

I'm using my ADC, AD9268 for an application where the clock has to be programmable over a wide frequency range. So I've decided to use AD9517-3 for clocking the ADC. But I don't want to sacrifice the ADC SNR /ENOB performance.
I used the ADISIMCLK v1.7 software for designing/optimising the loop filter for AD9517. 
I did the simulation in two ways: (1.) using the internal VCO of AD9517-3 and (2.) using an external VCO.
In the internal VCO case the jitter performance was not upto the requirement (424fs, SNR=71.49dB), whereas with external VCO the jitter improved to 258fs, SNR=75.8dB. The phase noise of internal VCO must be bad when compared to the external VCO case.
But both the results are far off from the specification. AD9268 is havnig 78dB SNR and ENOB of 12.7bits @ 70MHz.
Is there any other clock synthesiser ICs available which can meet the requirement?

Regards,

Vishnu R.

Parents
  • Hi,

    Didn't get any replies!!!

    Is there any evaluation results of ADC SNR performance using AD9517?

    Regards,

    Vishnu R

  • 0
    •  Analog Employees 
    on Oct 31, 2018 1:46 PM over 2 years ago in reply to Vishnu

    Hello Vishnu,

    I'm sorry for the delay in getting back to you.

    Basically you need a chip that can clean up an input clock to make is suitable for the AD9268. I recommend you use AD9530 instead.

    Best regards

    Petre

  • Hi Petre,

    I'm using the latest version of ADISIMCLK v1.7.

    But I dont find AD9530 in this design tool.

    How can I estimate the clock jitter performance for my application?

    Do you have any evaluation results (SNR) of AD9268 using AD9530 as the clock driver.

    Regards,

    Vishnu R.

  • 0
    •  Analog Employees 
    on Nov 1, 2018 1:18 PM over 2 years ago in reply to Vishnu

    Hi Vishnu,

     

    Yes, unfortunately the ADIsimCLK does not deal with the AD9530 and the evaluation software lacks a simulation feature, so in order to evaluate the noise performance, one needs to have an evaluation board.

     So I suggest you look at the typical phase noise performance plots from the data sheet, figure 9 to figure 14. Figure 14 is the most relevant plot for your application. The output frequency is 2.58 GHz which will need to be scaled to 70 MHz to be relevant. This is done by computing 20*log10(70/2580) = -31.33 dBc/Hz to get the scaling offset. This offset is applied ubiquitously to all data points in the plot. The exception is any point that scales below -165 dBc/Hz. This is the noise floor of the output drivers which is the lower limit of the phase noise.

     We do not have a characterization of the AD9268 performance when clocked from the AD9530. You can certainly take an AD9530 eval board and couple it to an AD9268 eval board and verify the performance

    Best regards

    Petre

  • Hi Petre,

    Thank you for very much  the information.

    We have decided to order the evaluation board for AD9530 (AD9530/PCBZ).

    But the chip is not available for purchase (I checked Digikey and Mouser).

    Can I interface the CML output of AD9530 directly to the ADC clock input with a 100Ohm resistor in parallel, like LVDS?

    Regards,

    Vishnu R

Reply Children
  • 0
    •  Analog Employees 
    on Nov 2, 2018 6:58 PM over 2 years ago in reply to Vishnu

    Hi Vishnu,

    In looking at the differential clock input specification of the AD9268, the differential input voltage range is 0.3 Vp-p - 3.6 Vp-p, which translates to single ended swings of 150 mVp-p – 1.8Vp-p. The common mode input range is 0.9V – 1.4 V and it can be internally generated at 0.9V to support AC-coupled inputs.

    Looking at the AD9530 output specifications, the output differential swing (which is specified in terms equivalent to single ended swing) is a minimum of 590 mV and a maximum of 1.455V when considering all output driver settings, so the output driver swing is compatible for any of the CML output configurations. However, the common mode specifications (> 1.7 V)  are not compliant, so AC-coupling will need to be used. Using the below termination scheme will produce an output that is compatible with the AD9268.

    Also enable the internal terminations to improve impedance match traces.

     

    Best regards

    Petre

  • Hi Petre,

    We conducted AD9530-AD9268 evaluation in two different configuration.

    (1.) Single ended clocking

    (2.) Differential clocking.

    In the first method, we used the single ended output of evaluation board (Transforfer output) and fed that to the single ended input of AD9268 evaluation board (Transformer and schottky diode path). He we met the datasheet requirement of 79dBc SNR.

    In the second configuration, we fed the differential output of AD9530, CML outputs as shown in Figure 19 above. But the 50E resistors are placed in AD9530 PCB and equal length coaxial cables were used for interfacing to AD9268 PCB. But here we got only 72dBc SNR. That is 7dB degradation in SNR.

    Please advise.

    Regards,

    Vishnu R,

  • 0
    •  Analog Employees 
    on Feb 13, 2019 8:12 PM over 1 year ago in reply to Vishnu

    Hi Vishnu,

    I have studied both AD9530 and AD9268 evaluation boards.

    The AD9530 board has a balun on the output, so the signal you can take from J304 terminal is single ended. It is not a differential output. 

    The AD9268 board has also a balun in the single path, plus multiple capacitors and a 57.6 ohm to ground at the input.

    So practically, if you need to truly realize a differential connection, you need to modify a lot both the boards and make the connections between them from some pads of the components on these boards, not from the terminals. But the point is to replicate that figure 19.

    Best regards

    Petre