Clocks & Timers

Q&A

by RS89 Clocks & Timers

Started 7 days ago

27 0 0

Not Answered
Lower Frequency Readings using the external 16MHz crystal on the EVAL board 0
Not Answered

Hello, I am trying to confirm that when I change the "MCLK, Ref Clock Frequency" to 2 MHz and set the "System Clock" to "External Clock" that this is within the board and I do not need to apply an external Function Generator/External Clock. I've measured...

hardware EVAL-AD5933EBZ UG-364

27 0 0
by MagicSmoke247 Clocks & Timers

Latest 9 days ago by MagicSmoke247

119 2 0

Answered
Subject: AD9545 EVB — how do I make it boot with my configuration without a PC? +1
Answered

Hi, I have the AD9545 evaluation board configured through ACE, and working. It outputs what I need as long as the PC stays connected. It receives 49.152 mhz and outputs 10 mhz I want it to boot with the same configuration on its own, with no PC...

hardware ad9545 Clock ICs clock and timing ad4595 Show More

119 2 0
by alexisdupont1994 Clocks & Timers

Started 10 days ago

33 0 0

Not Answered
TX1 and TX2 recommanded matching network 0
Not Answered

Hi, we are planing to use the AD9375 in the frequency band of 300 to 1000Mhz. From the UG-992 p.252 , we have to use the following components for the following circuit (See images below). So, we have to use the B0322J5050AHF. From the component, it...

hardware software defined radio ad9375 rf and microwave

33 0 0
by APaul2024 Clocks & Timers

Started 10 days ago

37 0 0

Not Answered
SYNC behaviour is not consistent after every power cycle 0
Not Answered

Hi, We are trying to synchronize the CH5 output (10 MHz) of the HMC7044 on a custom board. Current Configuration: PLL1: Disabled PLL2: Enabled External VCXO input: 500 MHz OSCIN input: 10 MHz reference clock from an external oscillator FPGA generates...

Datasheet/Specs hmc7044 Clock ICs clock and timing sync Show More

37 0 0
by IndujhaS Clocks & Timers

Latest 14 days ago by pminc48
97 1 0
Answered
Clocking Output Logic Level - Reg +1
Answered

Dear Team, What are the logic levels for a single-ended CMOS output? Please confirm if the CMOS outputs use 1.8V logic levels, regardless of the operating supply voltage. Regards, Indujha S

hardware clock and timing Fanout Buffers ad9508

97 1 0
by howgoood Clocks & Timers

Latest 14 days ago by pminc48
157 3 0
Answered
ADCLK944 jitter +1
Answered

What is the jitter of ADCLK944 when the input signals are 10MHz and 100Mhz?

Datasheet/Specs clock buffer clock and timing Fanout Buffers adclk944 Show More

157 3 0
by DaveF62 Clocks & Timers

Started 15 days ago

47 0 0

Not Answered
Programming fails to lock 0
Not Answered

We are using a third party software program to run a test and lock this device. The test puts in a time value that is 5 seconds later than the elapsed time and then it checks to see if the alarm goes off when the elapsed time reaches the programmed time...

software clock and timing Real-Time Clocks DS1682

47 0 0
by vivek111 Clocks & Timers

Latest 19 days ago by vivek111

198 4 0

Answered
design related help +1
Answered

im using ltc6994-1 for a delay adding operation where my control and power for the circuit are in the same line that is fed to vin and v+ .due to this the timer has not finished startup yet so it doesnt see the rising edge at all. is there any way to...

LTC6994-1 hardware clock and timing Real-Time Clocks

198 4 0
by SongSunHah Clocks & Timers

Started 23 days ago

180 0 0

Not Answered
Production Testing Image Issue of ADRV2CRR-FMC and ADRV9009-ZU11EG 0
Not Answered

Hi, I have some problems when testing the ADRV2CRR-FMC+ADRV9009-ZU11EG EVB: First problem is that the latest production testing image file can't be extracted successfully after many times of trying, would you please help to check it? The version is...

software 2022 adrv9009 software defined radio ADRV9009-ZU11EG rf and microwave Show More

180 0 0
by BarisDylan Clocks & Timers

Started 24 days ago

146 0 0

Not Answered
SPI Communication issues (3-wire/SDIO) with AD9434 and AD9517-4 on Petalinux 2025.2 (Zynq) 0
Not Answered

Hello everyone, I am working on a design based on Analog Devices’ HDL project for the Zedboard, connected to an AD9434-FMC-500EBZ board (which includes an AD9434 ADC and an AD9517-4 clock synthesiser). I am having difficulty communicating via SPI under...

Analog to Digital Converters (ADCs) ad9434 software spi Clock ICs clock and timing ad9434-fmc-500ebz petalinux Petalinux 2025.2 Show More

146 0 0
by Adrioxo11 Clocks & Timers

Latest 30 days ago by pminc48
159 1 0
Answered
ADCLK925 output to CML GTY input +1
Answered

Hello ADI support team. We are using ADCLK925 to buffer a clock for PCIe link. ADCLK925 outputs will be supplied to CML input of an FPGA GTY REFCLK and SSD component REFCLK. The ADCLK925 explains that "The outputs of the ADCLK905/ ADCLK907/ADCLK925...

adclk925 GTY hardware clock and timing Fanout Buffers cml Show More

159 1 0
by pbgg Clocks & Timers

Latest 1 month ago by pbgg

200 2 0

Answered
AD9528 pll2 not locked pll1 bypass +1
Answered

AD9528 bypss pll1 vcxo use ESG 122.88Mhz， out 245.76Mhz AD9528 board wr buff=0000: 99 --- wr buff=0001: 00 --- wr buff=0001: 20 --- wr buff=000F: 01 --- wr buff=0101: 00 --- wr buff=0100: 01 --- wr buff=0103: 00 --- wr buff=0102: 01 --- wr buff=0105...

Clock Generation Devices software Clock ICs ad9528 clock and timing Show More

200 2 0
by DaoHop Clocks & Timers

Started 1 month ago

84 0 0

Not Answered
LVDS AC Coupled for CLK Output 0
Not Answered

Hello, We are working on HMC7044B, I see that there is the different in the way terimate of LVDS output driver between HMC7044 vs HMC7044B. I have 2 questions on this: 1. Is the different correct? 2. I need to transform the CLKOUT LVDS to sing-end SMA...

hardware Clock ICs clock and timing HMC7044B

84 0 0
by YongLawrence Clocks & Timers

Latest 1 month ago by REtz
175 1 0
Answered
Does max31343 support milliseconds? 0
Answered

Hardware: max31343 in AD-PQMON-SL Question: Does max31343 support milliseconds? If yes, what’s the register address for milliseconds? So I can add into max31343.h no-OS/drivers/rtc/max31343/max31343.h at main · analogdevicesinc/no-OS

hardware clock and timing address register MAX31343 Real-Time Clocks milliseconds Show More

175 1 0
by yoelbn83 Clocks & Timers

Started 1 month ago

117 0 0

Not Answered
HMC7044B 0
Not Answered

Hi I want to use HMC7044B as clock distributer. I want to drive the FIN pin with 125MHZ and disabling PLL1 and PLL2. I already implemented this setup and it works, but, I couldn't figure out what is the minimum frequency that I use for FIN in distribution...

hmc7044 hardware Clock ICs clock and timing HMC7044B Show More

117 0 0

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Q&A

Not Answered
Lower Frequency Readings using the external 16MHz crystal on the EVAL board 0
Not Answered

Answered
Subject: AD9545 EVB — how do I make it boot with my configuration without a PC? +1
Answered

Not Answered
TX1 and TX2 recommanded matching network 0
Not Answered

Not Answered
SYNC behaviour is not consistent after every power cycle 0
Not Answered

Answered
Clocking Output Logic Level - Reg +1
Answered

Answered
ADCLK944 jitter +1
Answered

Not Answered
Programming fails to lock 0
Not Answered

Answered
design related help +1
Answered

Not Answered
Production Testing Image Issue of ADRV2CRR-FMC and ADRV9009-ZU11EG 0
Not Answered

Not Answered
SPI Communication issues (3-wire/SDIO) with AD9434 and AD9517-4 on Petalinux 2025.2 (Zynq) 0
Not Answered

Answered
ADCLK925 output to CML GTY input +1
Answered

Answered
AD9528 pll2 not locked pll1 bypass +1
Answered

Not Answered
LVDS AC Coupled for CLK Output 0
Not Answered

Answered
Does max31343 support milliseconds? 0
Answered

Not Answered
HMC7044B 0
Not Answered

Q&A

Not Answered Lower Frequency Readings using the external 16MHz crystal on the EVAL board 0 Not Answered

Answered Subject: AD9545 EVB — how do I make it boot with my configuration without a PC? +1 Answered

Not Answered TX1 and TX2 recommanded matching network 0 Not Answered

Not Answered SYNC behaviour is not consistent after every power cycle 0 Not Answered

Answered Clocking Output Logic Level - Reg +1 Answered

Answered ADCLK944 jitter +1 Answered

Not Answered Programming fails to lock 0 Not Answered

Answered design related help +1 Answered

Not Answered Production Testing Image Issue of ADRV2CRR-FMC and ADRV9009-ZU11EG 0 Not Answered

Not Answered SPI Communication issues (3-wire/SDIO) with AD9434 and AD9517-4 on Petalinux 2025.2 (Zynq) 0 Not Answered

Answered ADCLK925 output to CML GTY input +1 Answered

Answered AD9528 pll2 not locked pll1 bypass +1 Answered

Not Answered LVDS AC Coupled for CLK Output 0 Not Answered

Answered Does max31343 support milliseconds? 0 Answered

Not Answered HMC7044B 0 Not Answered

Not Answered
Lower Frequency Readings using the external 16MHz crystal on the EVAL board 0
Not Answered

Answered
Subject: AD9545 EVB — how do I make it boot with my configuration without a PC? +1
Answered

Not Answered
TX1 and TX2 recommanded matching network 0
Not Answered

Not Answered
SYNC behaviour is not consistent after every power cycle 0
Not Answered

Answered
Clocking Output Logic Level - Reg +1
Answered

Answered
ADCLK944 jitter +1
Answered

Not Answered
Programming fails to lock 0
Not Answered

Answered
design related help +1
Answered

Not Answered
Production Testing Image Issue of ADRV2CRR-FMC and ADRV9009-ZU11EG 0
Not Answered

Not Answered
SPI Communication issues (3-wire/SDIO) with AD9434 and AD9517-4 on Petalinux 2025.2 (Zynq) 0
Not Answered

Answered
ADCLK925 output to CML GTY input +1
Answered

Answered
AD9528 pll2 not locked pll1 bypass +1
Answered

Not Answered
LVDS AC Coupled for CLK Output 0
Not Answered

Answered
Does max31343 support milliseconds? 0
Answered

Not Answered
HMC7044B 0
Not Answered