1. I am using AD9528 to generate clocks for AD9375.
2. Reference clock used is 10 MHz. Output Frequency of interest is 122.88 MHz(Device Clock) & 0.96 MHz (Sysref)
3. I followed this approach from the following Link.
https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9008-1-adrv9008-2-adrv9009/f/q-a/167648/adrv9008-1-sampling-freq-selection and the attached snipshot is for your reference.
4. Kindly let us know the external Loop filter components of PLL for this approach!
Hi,
it is not clear to me why you need the 10MHz reference clock to PLL1 at all. The 122.88MHz outputs are not phase aligned to 10MHz at all, so I question why you need the 10MHz.
Besides this, there is another AD9528 that should have outputs with better phase noise because the PLL2 feedback divider is only 20, not 169 as in your case:
Anyway, I propose you simply use the 122.88MHz VCXO to create the 122.88MHz outputs and the 960kHz SYSREFs. Just retime the SYSREFs based on divider output or PLL1 output to align them to DEVCLKs.
Use the loop filter components the AD9528 evaluation board has. See schematic of the board here: https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/EVAL-AD9528.html#eb-documentation
Or use the ADIsimCLK to create the configuration below and play with loop filter settings to obtain the characteristics you target
Petre
