Post Go back to editing

PLL LOOP Filter components - AD9528

1. I am using AD9528 to generate clocks for AD9375.

2. Reference clock used is 10 MHz. Output Frequency of interest is 122.88 MHz(Device Clock) & 0.96 MHz (Sysref)

3. I followed this approach from the following Link. and the attached snipshot is for your reference.

4. Kindly let us know the external Loop filter components of PLL for this approach!