I would like to know about ADIsimCLK that was provided by ADI as development tool.
We designed with ADIsimCLK ver 1.30.01 for AD9255-4.
Input Frequency = 10.000MHz
Loop Bandwidth = 500kHz
Design Frequency = 1600MHz
Master Divider = 5 (1600/5=320MHz)
Div = 32 ,8 & 4
OUT=10MHz, 40MHz, 80MHz
(In this case, actual output freq is 9.7MHz , PLL unlock)
Q1: Is there any problem the product with V1.30.10 settings?
A last ADIsimCLK revision might be 1.60.10.
Q2: What is the difference between 1.30.10 and 1.60.10.?
We know that 1.60.10 displays “C1=32.0pF” at LF terminal.
Q3: Could we change this C1 value by simulation software?
Why 1.30.10 doesn’t show this C1?
Q4. What can support by Ver 1.30.10? It's for a different revision device?
Why do these calculate different result?