I have a further question which is related to this matter.
I am using ADIsimCLK v1.70 to verify my proposed set-up for the AD9528.
I end up having a frequency of 1.28906GHz at the output of M1 (VCO freq 3.86719GHz, M1 = 3 (some small rounding errors)) which results in the error "Max M1 out freq is 1.25GHz". I cannot find an explicit reference to this limitation in the datasheet.
I plan to divide this down using the 8-bit channel dividers in the clock distribution part to be less than 1GHz at each output.
Is this an error in ADIsimCLK?
Should the limitation be placed after the channel divider (as per your reply)?
Is there a maximum frequency that the 8-bit channel dividers can be run at?
I have just noticed that this is actually explained here (Query in AD9371 Evaluation Board VCXO selection doc ).
I assume this is just a bug in ADIsimCLK. Can you please confirm?
Actually, the resonse you posted here Clock limitations on AD9528 not clear
Looks like it is a bug in ADIsimCLK. Moving it to clock and timing subspace for further comments.
It should not be M1 frequency as the dividers are after that. What is referred as limitation is output of AD9528. (Output 1 and Output 2 with a maximum frequency of 1.25 GHz, and 12 outputs up to 1 GHz )
looks like you answer my question.
Copying here so that this topic is complete.