Clocks & Timers

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by Jason110 Clocks & Timers

Latest 34 minutes ago by Jason110

85 4 0

Answered
The output cannot be synchronized with the input phase +1
Answered

Hi ,I did not use the AD9544 evaluation board. The circuit was designed by myself based on the AD9544 manual. I used ACE to export register parameters and wrote them to the AD9544 through the MCU. SPI communication has been implemented, REFBB reference...

ad9544 hardware Clock ICs clock and timing

85 4 0
by AbishekDevan Clocks & Timers

Latest 3 hours ago by AbishekDevan

44 2 0

Answered
ADCLK946BCPZ – No Differential Output with AC-Coupled Single-Ended Input +1
Answered

Dear Team, We are using the ADCLK946BCPZ clock fanout buffer to generate a 10 MHz differential LVPECL output . However, we are unable to observe any output switching on the device despite verifying the input signal and power supplies. Our input configuration...

hardware adclk946 clock and timing Fanout Buffers

44 2 0
by yeah Clocks & Timers

Latest 19 hours ago by pminc48
38 3 0
Answered
Looking AD9545 to build a clock generator system that needs a low-jitter 1 Hz. Currently, I split a 1PPS signal into two paths: one path goes to the 1PPS input of the AD9545, and the other path goes to the TIC reference. Using ACE, I configured the AD9545 +1
Answered

Looking AD9545 to build a clock generator system that needs a low-jitter 1 Hz. Currently, I split a 1PPS signal into two paths: one path goes to the 1PPS input of the AD9545, and the other path goes to the TIC reference. Using ACE, I configured the AD9545...

software Clock ICs clock and timing

38 3 0
by Katy1163_AC Clocks & Timers

Latest 3 days ago by Katy1163_AC

77 2 0

Not Answered
Successful syncing of 2 HMC7044 devices to ref clock 0
Not Answered

I am using 2 HMC7044 devices to sync 10 JESD204B DACs (AD9144) on a custom PCB. I plan to set up my sync circuit as shown in the block diagram attached. I have 3 main questions besides anything you might see as incorrect int he block diagram 1. Only the...

hmc7044 hardware Clock ICs clock and timing jesd204b synchronization Show More

77 2 0
by Mahi192 Clocks & Timers

Latest 3 days ago by pminc48
113 7 0
Answered
PLL Locking and the SYSREF +1
Answered

Hi team, We are configuring the AD9528 in SYSREF Mode 3 (Internal) to generate the SYSREF signal internally via software/hardware requests. Because we are not feeding an external SYSREF signal into Pin 70 and Pin 71 how should we physically terminate...

hardware Clock ICs ad9528 clock and timing

113 7 0
by shimizu-yasu Clocks & Timers

Started 4 days ago

28 0 0

Not Answered
ADCLK925 IBIS model 0
Not Answered

Hello I have several questions regarding the ADCLK925 IBIS model. According to the [Notes] section at the beginning of the model file, I understand that the Min and Max models are defined based only on voltage and temperature conditions. The combinations...

ibis model adclk925 Datasheet/Specs clock and timing Fanout Buffers Show More

28 0 0
by mmercan Clocks & Timers

Latest 5 days ago by pminc48
138 3 0
Answered
AD9528 SYSREF / SYNC polarity inversion for AD7768 active-low sync trigger +1
Answered

Hello Analog Devices team, I am using an AD9528BCPZ as a clock distribution device in a system with AD7768 ADCs . The MCU is an STM32F446ZET6 , and the firmware is generated in STM32CubeIDE. I have two AD9528BCPZ for one of is MCLK distribution and...

Analog to Digital Converters (ADCs) software Clock ICs ad9528 clock and timing clock distribution Show More

138 3 0
by dclarkESI Clocks & Timers

Started 7 days ago

40 0 0

Not Answered
Bringing Up Clocks with adi_hmc7044.c 0
Not Answered

Hardware AD9082_FMCA_EBZ HMC7044 ZCU102 Schematic: Link to Schematic of AD9082-FMCA-EBZ Software Yocto Linux adi_hmc7044.c adi_ad9082.c Description I'm trying to work with this ad9082-fmca-ebz board and am struggling...

hmc7044 software AD9082_API-Rel1.7.0 AD9082 ADI API Show More

40 0 0
by LucaBaldanzi Clocks & Timers

Started 11 days ago

68 0 0

Not Answered
HMC7044: CLKIN0 LVPECL vs. LVDS input configuration issue (Oscillator fails to start) 0
Not Answered

Hi, I have designed a custom PCB for an RF data acquisition board based on the AD9081. For the clock generation tree, I am using the HMC7044. The schematic (see attached) is inspired by the AD9081 evaluation board (PN: AD9081-FMCA-EBZ). I am currently...

hmc7044 hardware Clock ICs A/D and D/A Converter Combinations clock and timing Show More

68 0 0
by NickAlves Clocks & Timers

Latest 13 days ago by pminc48
61 1 0
Answered
ADF4030 Evaluation Board: SDP-K1 program firmware failed! +1
Answered

I am unable to communicate with the ADF4030 evaluation board through the SDP-K1 controller board provided by ADI. I keep getting stuck when I connect my PC to the SDP-K1 via USB-C, the ACE software gives me a: "SDP-K1 Program Firmware failed! Please use...

ADF4030 synchronizer software Clock ICs clock and timing clock ACE software 1.30.3369.1491 Show More

61 1 0

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Clocks & Timers

Answered
The output cannot be synchronized with the input phase +1
Answered

Answered
ADCLK946BCPZ – No Differential Output with AC-Coupled Single-Ended Input +1
Answered

Answered
Looking AD9545 to build a clock generator system that needs a low-jitter 1 Hz. Currently, I split a 1PPS signal into two paths: one path goes to the 1PPS input of the AD9545, and the other path goes to the TIC reference. Using ACE, I configured the AD9545 +1
Answered

Not Answered
Successful syncing of 2 HMC7044 devices to ref clock 0
Not Answered

Answered
PLL Locking and the SYSREF +1
Answered

Not Answered
ADCLK925 IBIS model 0
Not Answered

Answered
AD9528 SYSREF / SYNC polarity inversion for AD7768 active-low sync trigger +1
Answered

Not Answered
Bringing Up Clocks with adi_hmc7044.c 0
Not Answered

Not Answered
HMC7044: CLKIN0 LVPECL vs. LVDS input configuration issue (Oscillator fails to start) 0
Not Answered

Answered
ADF4030 Evaluation Board: SDP-K1 program firmware failed! +1
Answered

Answered
Looking AD9545 to build a clock generator system that needs a low-jitter 1 Hz. Currently, I split a 1PPS signal into two paths: one path goes to the 1PPS input of the AD9545, and the other path goes to the TIC reference. Using ACE, I configured the AD9545 +1
Answered

Answered
ADCLK946BCPZ – No Differential Output with AC-Coupled Single-Ended Input +1
Answered

Answered
PLL Locking and the SYSREF +1
Answered

Answered
AD9528 SYSREF / SYNC polarity inversion for AD7768 active-low sync trigger +1
Answered

Answered
The output cannot be synchronized with the input phase +1
Answered

Answered
System Clock +1
Answered

Answered
ADF4030 Evaluation Board: SDP-K1 program firmware failed! +1
Answered

Answered
ADCLK905 Additive Phase Noise Data & ADIsimCLK Results +1
Answered

Answered
Subject: AD9545 EVB — how do I make it boot with my configuration without a PC? +1
Answered

Answered
Clocking Output Logic Level - Reg +1
Answered

Clocks & Timers

Answered The output cannot be synchronized with the input phase +1 Answered

Answered ADCLK946BCPZ – No Differential Output with AC-Coupled Single-Ended Input +1 Answered

Answered Looking AD9545 to build a clock generator system that needs a low-jitter 1 Hz. Currently, I split a 1PPS signal into two paths: one path goes to the 1PPS input of the AD9545, and the other path goes to the TIC reference. Using ACE, I configured the AD9545 +1 Answered

Not Answered Successful syncing of 2 HMC7044 devices to ref clock 0 Not Answered

Answered PLL Locking and the SYSREF +1 Answered

Not Answered ADCLK925 IBIS model 0 Not Answered

Answered AD9528 SYSREF / SYNC polarity inversion for AD7768 active-low sync trigger +1 Answered

Not Answered Bringing Up Clocks with adi_hmc7044.c 0 Not Answered

Not Answered HMC7044: CLKIN0 LVPECL vs. LVDS input configuration issue (Oscillator fails to start) 0 Not Answered

Answered ADF4030 Evaluation Board: SDP-K1 program firmware failed! +1 Answered

Answered Looking AD9545 to build a clock generator system that needs a low-jitter 1 Hz. Currently, I split a 1PPS signal into two paths: one path goes to the 1PPS input of the AD9545, and the other path goes to the TIC reference. Using ACE, I configured the AD9545 +1 Answered

Answered ADCLK946BCPZ – No Differential Output with AC-Coupled Single-Ended Input +1 Answered

Answered PLL Locking and the SYSREF +1 Answered

Answered AD9528 SYSREF / SYNC polarity inversion for AD7768 active-low sync trigger +1 Answered

Answered The output cannot be synchronized with the input phase +1 Answered

Answered System Clock +1 Answered

Answered ADF4030 Evaluation Board: SDP-K1 program firmware failed! +1 Answered

Answered ADCLK905 Additive Phase Noise Data & ADIsimCLK Results +1 Answered

Answered Subject: AD9545 EVB — how do I make it boot with my configuration without a PC? +1 Answered

Answered Clocking Output Logic Level - Reg +1 Answered

Answered
The output cannot be synchronized with the input phase +1
Answered

Answered
ADCLK946BCPZ – No Differential Output with AC-Coupled Single-Ended Input +1
Answered

Answered
Looking AD9545 to build a clock generator system that needs a low-jitter 1 Hz. Currently, I split a 1PPS signal into two paths: one path goes to the 1PPS input of the AD9545, and the other path goes to the TIC reference. Using ACE, I configured the AD9545 +1
Answered

Not Answered
Successful syncing of 2 HMC7044 devices to ref clock 0
Not Answered

Answered
PLL Locking and the SYSREF +1
Answered

Not Answered
ADCLK925 IBIS model 0
Not Answered

Answered
AD9528 SYSREF / SYNC polarity inversion for AD7768 active-low sync trigger +1
Answered

Not Answered
Bringing Up Clocks with adi_hmc7044.c 0
Not Answered

Not Answered
HMC7044: CLKIN0 LVPECL vs. LVDS input configuration issue (Oscillator fails to start) 0
Not Answered

Answered
ADF4030 Evaluation Board: SDP-K1 program firmware failed! +1
Answered

Answered
Looking AD9545 to build a clock generator system that needs a low-jitter 1 Hz. Currently, I split a 1PPS signal into two paths: one path goes to the 1PPS input of the AD9545, and the other path goes to the TIC reference. Using ACE, I configured the AD9545 +1
Answered

Answered
ADCLK946BCPZ – No Differential Output with AC-Coupled Single-Ended Input +1
Answered

Answered
PLL Locking and the SYSREF +1
Answered

Answered
AD9528 SYSREF / SYNC polarity inversion for AD7768 active-low sync trigger +1
Answered

Answered
The output cannot be synchronized with the input phase +1
Answered

Answered
System Clock +1
Answered

Answered
ADF4030 Evaluation Board: SDP-K1 program firmware failed! +1
Answered

Answered
ADCLK905 Additive Phase Noise Data & ADIsimCLK Results +1
Answered

Answered
Subject: AD9545 EVB — how do I make it boot with my configuration without a PC? +1
Answered

Answered
Clocking Output Logic Level - Reg +1
Answered